Memory and IO - wgrzegorz/c5xtools GitHub Wiki

Memory and I/O Spaces

Normative source: SPRU056D, chapter 8 (Memory). The register names and addresses below are transcribed from the memory-mapped register map in that chapter (Table 8-13).

The TMS320C5x uses an enhanced Harvard architecture: separate buses reach separate memory spaces, so a program fetch and a data access can proceed at the same time. The program bus (PB) carries instruction words and program-space operands; the data read bus (DB) carries data-space operands. Four address spaces are individually selectable:

Space	Size	Purpose
Program memory	64K words	instruction code, tables, immediate operands
Local data memory	64K words	data operated on by instructions
Global data memory	up to 32K words	data shared with other processors (overlays local data)
I/O space	64K ports	external memory-mapped peripherals, extra data storage

Each word is 16 bits. The four spaces together span a 224K-word address range. Within a space, RAM, ROM, EPROM, EEPROM, or memory-mapped peripherals may sit either on-chip or off-chip. In a single machine cycle the ALU can perform as many as three concurrent memory operations.

1. On-chip RAM blocks

Every 'C5x device carries 1056 words of dual-access RAM (DARAM), split into three fixed blocks, plus a device-dependent amount of single-access RAM (SARAM). DARAM can be read and written in the same machine cycle. SARAM needs a full machine cycle for one read or one write, but the CPU can access one SARAM block while accessing another in the same cycle.

Block	Words	Default location (local data)	Note
B0	512	0100h-02FFh	movable to program space FE00h-FFFFh
B1	512	0300h-04FFh	always in local data space
B2	32	0060h-007Fh	scratch-pad RAM, dual-access

Block B2 is the 32-word scratch-pad; it holds overhead variables so the larger blocks are not fragmented, and it can be reached through the memory-mapped addressing mode or any other data-memory addressing mode.

The CNF bit and block B0

DARAM block B0 is the only block that can move between spaces. At reset it lives in local data memory at 0100h-02FFh. Setting the CNF bit in status register ST1 remaps B0 into program space at FE00h-FFFFh; clearing CNF returns it to data space. When CNF = 1 the data-space range 0100h-02FFh reads as reserved.

    SETC  CNF            ; map B0 into program space (FE00h-FFFFh)
    CLRC  CNF            ; return B0 to data space (0100h-02FFh)

SARAM is made resident in program space by setting the RAM bit in the PMST, and resident in data space by setting the OVLY bit in the PMST:

    OPL   #010h, PMST    ; RAM bit: SARAM resident in program space

At reset the device configuration is set by the MP/MC pin. A high level selects microprocessor mode (on-chip ROM not addressed, execution starts off-chip); a low level selects microcomputer mode (on-chip ROM enabled, execution starts from it). The MP/MC pin is sampled only at reset; afterwards the MP/MC bit in the PMST can change the configuration in software.

2. Program memory

Program memory addresses up to 64K 16-bit words and holds instruction code, tables, and immediate operands. It is accessed over the program address bus. The program counter (PC) drives the bus for instruction fetches and is also loaded for program-memory operand access by TBLR, TBLW, BLPD, BLDP, and by the second-multiplicand fetches of MAC, MACD, MADS, and MADD.

The interrupt vectors live in program space. At reset they map to 0000h, and reset always fetches its vector at 0000h because reset loads the interrupt vector pointer (IPTR) in the PMST with 0. After reset the IPTR can relocate the remaining vectors to the start of any 2K-word page in program space:

    OPL   #05800h, PMST  ; remap interrupt vectors to start at 5800h

Two words are reserved at each vector location for a branch to the interrupt service routine. The address visibility (AVIS) bit in the PMST, enabled after reset, drives the program address out to the device pins for tracing and can be cleared to lower power and noise once debugging is done. A program-memory protection feature prevents an instruction fetched from off-chip memory from reading or writing on-chip program memory.

3. Local data memory

Local data memory addresses up to 64K 16-bit words. At reset the 1056 words of DARAM are mapped into local data space. Block B0 can be moved to program space with CNF; SARAM can be overlaid into data space with the OVLY bit in the PMST.

Any location in the range 0000h-0800h not mapped to on-chip memory is an on-chip reserved location. The lowest part of the space, data page 0, holds the memory-mapped registers and ports:

Range	Contents
0000h-004Fh	on-chip memory-mapped registers (CPU and peripheral)
0050h-005Fh	memory-mapped I/O ports (16 ports)
0060h-007Fh	scratch-pad RAM (DARAM block B2)

Data page 0 is organized into five groups of registers: CPU registers, peripheral registers, a test/emulation reserved area, the I/O ports, and the scratch-pad RAM. The CPU registers are accessed with zero wait states. The peripheral registers sit on the TI Bus and require one wait state. Writing to the test/emulation reserved area can change the device operational mode and so can affect the application.

Data-space page-0 map

4. Memory-mapped register map (0000h-005Fh)

The registers below are transcribed from Table 8-13 of SPRU056D. Addresses are in hexadecimal. Only the entries named in the source are listed; the serial, peripheral, and reserved areas appear in the source as address ranges rather than individually named registers, so they are given as ranges here.

Address	Name	Description
0000h-0003h	---	Reserved
0004h	IMR	Interrupt mask register
0005h	GREG	Global memory allocation register
0006h	IFR	Interrupt flag register
0007h	PMST	Processor mode status register
0008h	RPTC	Repeat counter register
0009h	BRCR	Block repeat counter register
000Ah	PASR	Block repeat program address start register
000Bh	PAER	Block repeat program address end register
000Ch	TREG0	Temporary register 0 (multiplicand)
000Dh	TREG1	Temporary register 1 (dynamic shift count)
000Eh	TREG2	Temporary register 2 (bit pointer in dynamic bit test)
000Fh	DBMR	Dynamic bit manipulation register
0010h	AR0	Auxiliary register 0
0011h	AR1	Auxiliary register 1
0012h	AR2	Auxiliary register 2
0013h	AR3	Auxiliary register 3
0014h	AR4	Auxiliary register 4
0015h	AR5	Auxiliary register 5
0016h	AR6	Auxiliary register 6
0017h	AR7	Auxiliary register 7
0018h	INDX	Index register
0019h	ARCR	Auxiliary register compare register
001Ah	CBSR1	Circular buffer 1 start register
001Bh	CBER1	Circular buffer 1 end register
001Ch	CBSR2	Circular buffer 2 start register
001Dh	CBER2	Circular buffer 2 end register
001Eh	CBCR	Circular buffer control register
001Fh	BMAR	Block move address register
0020h-0023h	---	Memory-mapped serial port registers
0024h-002Ah	---	Memory-mapped peripheral registers
002Bh-002Fh	---	Reserved for test/emulation
0030h-0037h	---	Memory-mapped serial port registers
0038h-004Fh	---	Reserved
0050h-005Fh	---	Memory-mapped I/O ports
0060h-007Fh	---	Scratch-pad RAM (DARAM block B2)

The register file at 0010h-001Fh (AR0..AR7, INDX, ARCR, CBSR1, CBER1, CBSR2, CBER2, CBCR, BMAR) backs indirect and circular addressing, described on the Addressing Modes page. The four MMR-addressing instructions (LAMM, SAMM, LMMR, SMMR) reach any of these addresses with the nine high address bits forced to 0, without disturbing the DP.

5. Global data memory

For multiprocessing, part of the data space can be declared global and shared with other processors over the BR (bus request) and READY signals. The global memory allocation register (GREG) selects how much of the top of data space is global. GREG is 8 bits, memory-mapped at data address 0005h and connected to the eight LSBs of the internal data bus; the upper eight bits of 0005h are unused and read as 1s.

The value in GREG sets the global size, from 256 to 32K words, taken from the top of the 64K data space:

GREG value (binary)	Local range	Local words	Global range	Global words
0000 00XX	0000h-FFFF	65536	---	0
1000 0000	0000h-7FFF	32768	8000h-FFFF	32768
1100 0000	0000h-BFFF	49152	C000h-FFFF	16384
1110 0000	0000h-DFFF	57344	E000h-FFFF	8192
1111 0000	0000h-EFFF	61440	F000h-FFFF	4096
1111 1000	0000h-F7FF	63488	F800h-FFFF	2048
1111 1100	0000h-FBFF	64512	FC00h-FFFF	1024
1111 1110	0000h-FDFF	65024	FE00h-FFFF	512
1111 1111	0000h-FEFF	65280	FF00h-FFFF	256

(X = don't-care bit.) GREG values other than those above produce fragmented maps and must be avoided. When an address falls in the global region, BR is asserted low with DS; external logic arbitrates and returns READY. Unlike a DMA transfer, reading or writing global memory does not halt either processor.

6. I/O space

I/O space provides 64K 16-bit parallel ports, multiplexed over the same address and data bus used for program and data accesses. All 64K ports are reached with the IN and OUT instructions:

    IN   DAT7, 0FFFEh    ; read port 65534 into data memory
    OUT  DAT7, 0FFFFh    ; write data memory to port 65535

Sixteen of the ports are additionally memory-mapped into data page 0 at 0050h-005Fh. Those sixteen can be reached either by IN/OUT or by any instruction that reads or writes data memory; for example SAMM to a mapped port behaves like an OUT (the IS line goes active). Mapped port addresses reside off-chip and are subject to external and software wait states. I/O access times are tuned by the software wait-state registers (IOWSR and CWSR); the BIG bit in CWSR sets how the I/O space is partitioned.

The LMMR and SMMR instructions move blocks between data memory and an I/O port. LMMR copies from data memory to a port; SMMR copies from a port into data memory. Both work with the repeat instructions for block transfers:

    LDP   #0             ; DP = 0
    RPT   #63
    LMMR  50h, #800h     ; 64 words from table at 800h out to port 50h

7. Direct memory access (DMA)

The 'C5x supports DMA of external memory and of on-chip SARAM so another processor can read or write while one or more 'C5x devices are halted. External memory access is controlled through HOLD and HOLDA; on-chip RAM access adds the BR, R/W, STRB, and IAQ signals. In a master-slave setup the master drives the slave's HOLD low (through its XF pin), the slave tristates its buses and asserts HOLDA, and the master then drives BR low to reach the SARAM, with the slave acknowledging on IAQ. During external DMA the address decode uses only A13-A0 (A14 and A15 are ignored), so the SARAM aliases at several ranges. DMA to on-chip SARAM is not supported in concurrent hold mode (HM = 0), nor during reset.

8. Memory-to-memory moves

Several instructions move blocks efficiently between the spaces, usually paired with RPT or RPTZ. One address comes from the data address generator; the other comes from a long immediate constant or from the BMAR.

Instruction	Move
BLDD	data memory to data memory
BLDP	data memory to program memory
BLPD	program memory to data memory
TBLR	program memory to data memory (source address in accumulator)
TBLW	data memory to program memory (destination address in accumulator)
DMOV	copy a word to the next higher on-chip RAM location while operating on it

DMOV implements the z^-1 delay used by convolution and filtering. It runs in one cycle in dual-access RAM (an extra cycle in SARAM), is contiguous across the B0 and B1 boundary, and cannot operate on external data memory. LTD, MACD, and MADD use the DMOV function.

9. Boot loader

Several 'C5x devices contain a boot-loader program in on-chip ROM whose job is to copy code from an external source into program memory at power-up. If the MP/MC pin is low at a hardware reset, execution begins at 0000h in on-chip ROM, which branches to the boot loader. Before loading, the boot loader disables interrupts (INTM = 1), maps B0 into program space (CNF = 1), maps the SARAM into program space (RAM = 1, OVLY = 0), enables all program and data space with seven wait states, and enables 32K of global data memory at 8000h-FFFFh (disabled again once the transfer is done).

The loader reads the boot routine selection word from global data location FFFFh (driving BR and DS low); only its low 8 bits matter. The low nibble chooses the mode:

Selection word (low bits)	Boot mode
0000	8-bit serial
0100	16-bit serial
1000	8-bit parallel I/O
1100	16-bit parallel I/O
01 (with 6-bit SRC page)	8-bit parallel EPROM
10 (with 6-bit SRC page)	16-bit parallel EPROM
11 (with 6-bit ADDR page)	warm boot

For serial and parallel modes the transferred stream begins with a 16-bit destination address, then a 16-bit length word N (N = number of 16-bit words minus 1), then the N code words; the loader branches to the destination when it finishes. Parallel I/O mode transfers asynchronously through I/O port 50h using a BIO/XF handshake. Warm boot runs the loader but moves no code: control simply passes to an entry address whose six MSBs come from the ADDR field. The 'C57 also offers an HPI boot mode, selected by connecting HINT to INT3, which hands control to the on-chip HPI RAM at 8800h.