Normative source: SPRU056D, chapter 6 (Assembly Language Instructions). Opcodes are additionally cross-checked against the toolchain's own instruction table (include/c5x_isa.h).

This page is the complete instruction set: it defines the notation, groups the instructions by function, and then gives one section for every instruction in alphabetical order. Jump straight to any mnemonic from the sidebar.

The toolchain's instruction table holds 229 entries: 228 are assembler mnemonics, counting every addressing variant and enhanced form, plus one internal format-group sentinel that is not a user instruction. A few mnemonics (for example ADD, AND, MPY, SUB) appear with a placeholder base opcode in the table and are resolved to a form-specific encoding by the assembler; the detail pages note this where it applies. The functional tables below list the primary instructions as the manual groups them.

Every entry on the detail pages gives:

Operand notation (dma, ind, ARn, shift, pma, immediate #k and #lk) is defined on the Addressing Modes and Assembler Syntax pages.

From SPRU056D Table 6-1, the symbols that appear in the Opcode field of the detail entries:

The TP field encodes:

  TP     Condition
  00     BIO pin low
  01     TC = 1
  10     TC = 0  (NTC)
  11     none of the above

The manual sorts the instruction set into seven classes (SPRU056D Tables 6-4 through 6-10). Each instruction's full entry is on the alphabetical detail page for its first letter.

The map below colors the 256 possible high bytes (bits 15-8 of the instruction word) by the functional group that owns them, giving a one-glance picture of how the opcode space is carved up.

Load, store, add, subtract, and the accumulator shifts and logicals that read or write data memory through the CALU.

ABS   ADCB  ADD   ADDB  ADDC  ADDS  ADDT  AND   ANDB  BSAR
CMPL  CRGT  CRLT  EXAR  LACB  LACC  LACL  LACT  LAMM  NEG
NORM  OR    ORB   ROL   ROLB  ROR   RORB  SACB  SACH  SACL
SAMM  SATH  SATL  SBB   SBBB  SFL   SFLB  SFR   SFRB  SUB
SUBB  SUBC  SUBS  SUBT  XOR   XORB  ZALR  ZAP

Load, store, modify and compare the auxiliary registers and set the data page.

ADRK  CMPR  LAR   LDP   MAR   SAR   SBRK

Read-modify-write logic on a data-memory word against an immediate or the DBMR.

AND   APL   CPL   LPH   LT    OPL   OR    SPLK  XPL

Load TREG, multiply, accumulate the product, and move or shift the product.

LTA   LTD   LTP   LTS   MAC   MACD  MADD  MADS  MPY   MPYA
MPYS  MPYU  PAC   SPAC  SPH   SPL   SPM   SQRA  SQRS  ZPR

Unconditional and conditional branches, calls, returns, and conditional execution.

B     BACC  BACCD BANZ  BANZD BCND  BCNDD BD    CALA  CALAD
CALL  CALLD CC    CCD   INTR  NMI   RET   RETC  RETCD RETD
RETE  RETI  TRAP  XC

Block moves, table reads and writes, data moves, memory-mapped register moves, and port I/O.

BLDD  BLDP  BLPD  DMOV  IN    LMMR  OUT   SMMR  TBLR  TBLW

Status-bit control, repeat setup, stack pushes and pops, bit tests, and the idle and no-operation instructions.

BIT   BITT  CLRC  IDLE  IDLE2 LST   NOP   POP   POPD  PSHD
PUSH  RPT   RPTB  RPTZ  SETC  SST

Absolute value of the accumulator.

Syntax: ABS

Operation: (PC) + 1 -> PC; |(ACC)| -> ACC; 0 -> C

Operands: None.

Opcode:

 15 14 13 12 | 11 10  9  8 |  7  6  5  4 |  3  2  1  0
  1  0  1  1 |  1  1  1  0 |  0  0  0  0 |  0  0  0  0    = 0xBE00

Toolchain base 0xBE00 agrees with the manual graphic.

Status bits: Affected by OVM; not affected by SXM; affects C and OV. With OVM = 0 the ABS of 8000 0000h stays 8000 0000h; with OVM = 1 it becomes 7FFF FFFFh; OV is set in either case.

Words / Cycles: 1 word; 1 cycle for a single on-chip (DARAM) execution.

Cycle class: I - see Instruction Timing.

Cycle timing (SPRU056D ch. 6):

Cycles for a Single Instruction:

Cycles for a Repeat (RPT) Execution:

Example:

    ABS                 ; ACC = FFFF FFFFh becomes 1h, C is cleared

Add the accumulator buffer and carry to the accumulator.

Syntax: ADCB

Operation: (PC) + 1 -> PC; (ACC) + (ACCB) + (C) -> ACC

Operands: None.

Opcode:

 15 14 13 12 | 11 10  9  8 |  7  6  5  4 |  3  2  1  0
  1  0  1  1 |  1  1  1  0 |  0  0  0  1 |  0  0  0  1    = 0xBE11

Toolchain base 0xBE11 agrees with the manual graphic.

Status bits: Affected by OVM; affects C and OV. C is set on a carry out of the addition, otherwise cleared. ACCB is left unchanged.

Words / Cycles: 1 word; 1 cycle (DARAM, single).

Cycle class: I - see Instruction Timing.

Cycle timing (SPRU056D ch. 6):

Cycles for a Single Instruction:

Cycles for a Repeat (RPT) Execution:

Example:

    ADCB                ; ACC = ACC + ACCB + C

Add a shifted data-memory value or an immediate constant to the accumulator.

This is the general ADD entry. The toolchain also exposes the individual forms as ADDH (shift of 16), ADDI (direct/indirect with shift), ADDK (short immediate), and ADLK (long immediate); each has its own section below.

Syntax:

    Direct:            ADD dma [,shift]
    Indirect:          ADD {ind} [,shift] [,ARn]
    Short immediate:   ADD #k
    Long immediate:    ADD #lk [,shift]

Operation:

• Direct or indirect: (ACC) + ((dma) x 2^shift) -> ACC
• Short immediate: (ACC) + k -> ACC
• Long immediate: (ACC) + (lk x 2^shift) -> ACC

Operands: 0 <= dma <= 127; 0 <= shift <= 16 (defaults to 0); 0 <= n <= 7; 0 <= k <= 255; -32768 <= lk <= 32767.

Opcode: The manual gives one graphic per form:

 direct, with shift:        0 0 1 0  <-SHFT->  0  <----- dma ----->   = 0x2000
 indirect, with shift:      0 0 1 0  <-SHFT->  1  <- see Section 5.2  = 0x2080
 direct, shift of 16:       0 1 1 0  0 0 0 1   0  <----- dma ----->   = 0x6100
 indirect, shift of 16:     0 1 1 0  0 0 0 1   1  <- see Section 5.2  = 0x6180
 short immediate:           1 0 1 1  1 0 0 0   <--- 8-bit constant -> = 0xB800
 long immediate, w/ shift:  1 0 1 1  1 1 1 1   1 0 0 1  <-SHFT->      = 0xBF90
                            (second word = 16-bit constant)

The toolchain stores 0x0000 as the base for the umbrella mnemonic ADD; that value is a placeholder and does not match any single manual graphic, because the assembler resolves ADD to one of the form-specific encodings above (which the toolchain also names ADDI, ADDH, ADDK, ADLK).

Status bits: Affected by OVM and SXM (direct, indirect, long immediate) or OVM only (short immediate); affects C and OV. For a shift of 16 the C bit is set on carry but is not cleared when there is no carry, so a 32-bit accumulation produces a single correct carry.

Words / Cycles: 1 word (direct, indirect, short immediate) or 2 words (long immediate); 1 cycle for a single direct/indirect/short execution, 2 cycles for long immediate (DARAM). The short- and long-immediate forms are not repeatable.

Cycle class: IIA (ADD); I (ADD #k); III (ADD #lk) - see Instruction Timing.

Cycle timing (SPRU056D ch. 6):

For the short and long immediate addressing modes, the ADD instruction is not repeatable.

Cycles for a Single Instruction (direct or indirect addressing):

• If the operand and the code are in the same SARAM block

Cycles for a Repeat (RPT) Execution (direct or indirect addressing):

• If the operand and the code are in the same SARAM block

Cycles for a Single Instruction (short immediate addressing):

Cycles for a Single Instruction (long immediate addressing):

Example:

    ADD   DAT1,1        ; ACC += Data(DAT1) << 1  (DP = 6)
    ADD   #1111h,1      ; ACC += 1111h << 1  (long immediate)

Add the accumulator buffer to the accumulator.

Syntax: ADDB

Operation: (PC) + 1 -> PC; (ACC) + (ACCB) -> ACC

Operands: None.

Opcode:

 15 14 13 12 | 11 10  9  8 |  7  6  5  4 |  3  2  1  0
  1  0  1  1 |  1  1  1  0 |  0  0  0  1 |  0  0  0  0    = 0xBE10

Toolchain base 0xBE10 agrees with the manual graphic.

Status bits: Affected by OVM; affects C and OV. C is set on a carry, otherwise cleared. ACCB is left unchanged.

Words / Cycles: 1 word; 1 cycle (DARAM, single).

Cycle class: I - see Instruction Timing.

Cycle timing (SPRU056D ch. 6):

Cycles for a Single Instruction:

Cycles for a Repeat (RPT) Execution:

Example:

    ADDB                ; ACC = 1234h + ACCB(2h) = 1236h

Add a data-memory value and the carry to the accumulator (sign extension suppressed).

Syntax:

    Direct:     ADDC dma
    Indirect:   ADDC {ind} [,ARn]

Operation: (PC) + 1 -> PC; (ACC) + (dma) + (C) -> ACC

Operands: 0 <= dma <= 127; 0 <= n <= 7; ind: {* *+ *- *0+ *0- *BR0+ *BR0-}.

Opcode:

 direct:    0 1 1 0  0 0 0 0   0  <----- dma ----->      = 0x6000
 indirect:  0 1 1 0  0 0 0 0   1  <- see Section 5.2      = 0x6080

Toolchain base 0x6000 agrees with the manual direct graphic.

Status bits: Affected by OVM; not affected by SXM; affects C and OV. Useful in multiple-precision arithmetic.

Words / Cycles: 1 word; 1 cycle for a DARAM operand (single execution).

Cycle class: IIA - see Instruction Timing.

Cycle timing (SPRU056D ch. 6):

Cycles for a Single Instruction:

• If the operand and the code are in the same SARAM block

Cycles for a Repeat (RPT) Execution:

• If the operand and the code are in the same SARAM block

Example:

    ADDC  DAT0          ; ACC += Data(DAT0) + C  (DP = 6)

Add a data-memory value to the high half of the accumulator (shift of 16).

This is the shift-of-16 form of ADD; see ADD for the shared operation and status description.

Syntax:

    Direct:     ADD dma, 16
    Indirect:   ADD {ind}, 16 [,ARn]

Operation: (PC) + 1 -> PC; (ACC) + ((dma) x 2^16) -> ACC

Operands: 0 <= dma <= 127; 0 <= n <= 7.

Opcode:

 direct:    0 1 1 0  0 0 0 1   0  <----- dma ----->      = 0x6100
 indirect:  0 1 1 0  0 0 0 1   1  <- see Section 5.2      = 0x6180

Toolchain base 0x6100 agrees with the manual "shift of 16" graphic for ADD.

Status bits: Affected by OVM and SXM; affects C and OV. On a shift of 16 the C bit is set on carry but not cleared otherwise (see ADD).

Words / Cycles: 1 word; 1 cycle for a DARAM operand (single execution).

Cycle class: see Instruction Timing.

Example:

    ADD   DAT1,16       ; ACC += Data(DAT1) << 16

Add a shifted data-memory value to the accumulator (direct/indirect, shift 0-15).

This is the direct/indirect-with-shift form of ADD; see ADD for the shared operation and status description.

Syntax:

    Direct:     ADD dma [,shift]
    Indirect:   ADD {ind} [,shift] [,ARn]

Operation: (PC) + 1 -> PC; (ACC) + ((dma) x 2^shift) -> ACC

Operands: 0 <= dma <= 127; 0 <= shift <= 16 (defaults to 0); 0 <= n <= 7.

Opcode:

 direct:    0 0 1 0  <-SHFT->  0  <----- dma ----->      = 0x2000
 indirect:  0 0 1 0  <-SHFT->  1  <- see Section 5.2      = 0x2080

Toolchain base 0x2000 agrees with the manual "direct addressing with shift" graphic for ADD.

Status bits: Affected by OVM and SXM; affects C and OV.

Words / Cycles: 1 word; 1 cycle for a DARAM operand (single execution).

Cycle class: see Instruction Timing.

Example:

    ADD   *+,0,AR0      ; ACC += Data(*AR), no shift, then point ARP to AR0

Add a short immediate constant to the accumulator.

This is the short-immediate form of ADD; see ADD for the shared operation and status description.

Syntax: ADD #k

Operation: (PC) + 1 -> PC; (ACC) + k -> ACC

Operands: 0 <= k <= 255 (an 8-bit positive constant).

Opcode:

 15 14 13 12 | 11 10  9  8 |  7  6  5  4  3  2  1  0
  1  0  1  1 |  1  0  0  0 |  <--- 8-bit constant --->     = 0xB800

Toolchain base 0xB800 agrees with the manual "short immediate" graphic for ADD.

Status bits: Affected by OVM; affects C and OV. The addition is unaffected by SXM, and no shift may be specified.

Words / Cycles: 1 word; 1 cycle (DARAM, single). Not repeatable.

Cycle class: see Instruction Timing.

Example:

    ADD   #1h           ; ACC = 2h + 1h = 3h

Add an unsigned data-memory value to the accumulator (sign extension suppressed).

Syntax:

    Direct:     ADDS dma
    Indirect:   ADDS {ind} [,ARn]

Operation: (PC) + 1 -> PC; (ACC) + (dma) -> ACC, where (dma) is treated as an unsigned 16-bit number.

Operands: 0 <= dma <= 127; 0 <= n <= 7; ind: {* *+ *- *0+ *0- *BR0+ *BR0-}.

Opcode:

 direct:    0 1 1 0  0 0 1 0   0  <----- dma ----->      = 0x6200
 indirect:  0 1 1 0  0 0 1 0   1  <- see Section 5.2      = 0x6280

Toolchain base 0x6200 agrees with the manual direct graphic.

Status bits: Affected by OVM; not affected by SXM; affects C and OV. Produces the same result as ADD with SXM cleared and a shift of 0.

Words / Cycles: 1 word; 1 cycle for a DARAM operand (single execution).

Cycle class: IIA - see Instruction Timing.

Cycle timing (SPRU056D ch. 6):

Cycles for a Single Instruction:

• If the operand and the code are in the same SARAM block

Cycles for a Repeat (RPT) Execution:

• If the operand and the code are in the same SARAM block

Example:

    ADDS  DAT0          ; ACC = 0000 0003h + F006h = 0000 F009h  (DP = 6)

Add a data-memory value shifted by TREG1 to the accumulator.

Syntax:

    Direct:     ADDT dma
    Indirect:   ADDT {ind} [,ARn]

Operation: (PC) + 1 -> PC; (ACC) + ((dma) x 2^TREG1(3-0)) -> ACC. If SXM = 0 the dma is not sign-extended; if SXM = 1 it is.

Operands: 0 <= dma <= 127; 0 <= n <= 7; ind: {* *+ *- *0+ *0- *BR0+ *BR0-}.

Opcode:

 direct:    0 1 1 0  0 0 1 1   0  <----- dma ----->      = 0x6300
 indirect:  0 1 1 0  0 0 1 1   1  <- see Section 5.2      = 0x6380

Toolchain base 0x6300 agrees with the manual direct graphic.

Status bits: Affected by OVM, SXM, and TRM; affects C and OV. The shift count is the 4 LSBs of TREG1 (0 to 15 bits).

Words / Cycles: 1 word; 1 cycle for a DARAM operand (single execution).

Cycle class: IIA - see Instruction Timing.

Cycle timing (SPRU056D ch. 6):

Cycles for a Single Instruction:

• If the operand and the code are in the same SARAM block

Cycles for a Repeat (RPT) Execution:

• If the operand and the code are in the same SARAM block

Example:

    ADDT  DAT127        ; ACC += Data(027Fh) << TREG1(3-0)  (DP = 4, SXM = 0)

Add a long immediate constant (with shift) to the accumulator.

This is the long-immediate form of ADD; see ADD for the shared operation and status description.

Syntax: ADD #lk [,shift]

Operation: (PC) + 2 -> PC; (ACC) + (lk x 2^shift) -> ACC

Operands: -32768 <= lk <= 32767; 0 <= shift <= 16 (defaults to 0).

Opcode:

 15 14 13 12 | 11 10  9  8 |  7  6  5  4 |  3  2  1  0
  1  0  1  1 |  1  1  1  1 |  1  0  0  1 |  <-SHFT->      = 0xBF90
 (second word = 16-bit constant)

Toolchain base 0xBF90 agrees with the manual "long immediate with shift" graphic for ADD.

Status bits: Affected by OVM and SXM; affects C and OV.

Words / Cycles: 2 words; 2 cycles (DARAM, single). Not repeatable.

Cycle class: see Instruction Timing.

Example:

    ADD   #1111h,1      ; ACC += 1111h << 1 = 2222h added

Add a short immediate constant to the current auxiliary register.

Syntax: ADRK #k

Operation: (PC) + 1 -> PC; (current AR) + 8-bit positive constant -> current AR

Operands: 0 <= k <= 255.

Opcode:

 15 14 13 12 | 11 10  9  8 |  7  6  5  4  3  2  1  0
  0  1  1  1 |  1  0  0  0 |  <--- 8-bit constant --->     = 0x7800

Toolchain base 0x7800 agrees with the manual graphic.

Status bits: None affected. The add happens in the ARAU; all AR arithmetic is unsigned.

Words / Cycles: 1 word; 1 cycle (DARAM, single). Not repeatable.

Cycle class: I (ADRK #k) - see Instruction Timing.

Cycle timing (SPRU056D ch. 6):

The ADRK instruction is not repeatable.

Cycles for a Single Instruction:

Example:

    ADRK  #80h          ; AR5 = 4321h becomes 43A1h

Bitwise AND of a data-memory value or an immediate constant with the accumulator.

This is the general AND entry. The toolchain also exposes the forms as ANDI (direct/indirect) and ANDK (long immediate); each has its own section below.

Syntax:

    Direct:            AND dma
    Indirect:          AND {ind} [,ARn]
    Long immediate:    AND #lk [,shift]

Operation:

• Direct or indirect: (ACC(15-0)) AND (dma) -> ACC(15-0); 0 -> ACC(31-16)
• Long immediate: (ACC(30-0)) AND (lk x 2^shift) -> ACC

Operands: 0 <= dma <= 127; 0 <= n <= 7; lk: 16-bit constant; 0 <= shift <= 16.

Opcode: The manual gives one graphic per form:

 direct:                    0 1 1 0  1 1 1 0   0  <----- dma ----->   = 0x6E00
 indirect:                  0 1 1 0  1 1 1 0   1  <- see Section 5.2  = 0x6E80
 long immediate, w/ shift:  1 0 1 1  1 1 1 1   1 0 1 1  <-SHFT->      = 0xBFB0
 long immediate, shift 16:  1 0 1 1  1 1 1 0   1 0 0 0  0 0 1         = 0xBE81
                            (long immediate second word = 16-bit constant)

The toolchain stores 0x0000 as the base for the umbrella mnemonic AND; that value is a placeholder and does not match any single manual graphic, because the assembler resolves AND to one of the form-specific encodings above (also named ANDI and ANDK in the toolchain).

Status bits: Not affected by SXM (long immediate). No other status bits are listed as affected for the direct/indirect form.

Words / Cycles: 1 word (direct, indirect) or 2 words (long immediate); 1 cycle for a single direct/indirect execution, 2 cycles for long immediate (DARAM). The long-immediate form is not repeatable.

Cycle class: IIA (AND); III (AND #lk) - see Instruction Timing.

Cycle timing (SPRU056D ch. 6):

For the long immediate addressing modes, the AND instruction is not repeatable.

Cycles for a Single Instruction (direct or indirect addressing):

• If the operand and the code are in the same SARAM block.

Cycles for a Repeat (RPT) Execution (direct or indirect addressing):

• If the operand and the code are in the same SARAM block.

Cycles for a Single Instruction (long immediate addressing):

Example:

    AND   DAT16         ; ACC = 1234 5678h AND 00FFh = 0000 0078h (DP = 4)
    AND   #00FFh,4      ; ACC = 1234 5678h AND (00FFh << 4) = 0000 0670h

Bitwise AND of the accumulator buffer with the accumulator.

Syntax: ANDB

Operation: (PC) + 1 -> PC; (ACC) AND (ACCB) -> ACC

Operands: None.

Opcode:

 15 14 13 12 | 11 10  9  8 |  7  6  5  4 |  3  2  1  0
  1  0  1  1 |  1  1  1  0 |  0  0  0  1 |  0  0  1  0    = 0xBE12

Toolchain base 0xBE12 agrees with the manual graphic.

Status bits: None affected. ACCB is left unchanged.

Words / Cycles: 1 word; 1 cycle (DARAM, single).

Cycle class: I - see Instruction Timing.

Cycle timing (SPRU056D ch. 6):

Cycles for a Single Instruction:

Cycles for a Repeat (RPT) Execution:

Example:

    ANDB                ; ACC = 0F0F FFFFh AND 5555 5555h = 0505 5555h

Bitwise AND of a data-memory value with the accumulator low half (direct/indirect).

This is the direct/indirect form of AND; see AND for the shared operation and status description.

Syntax:

    Direct:     AND dma
    Indirect:   AND {ind} [,ARn]

Operation: (PC) + 1 -> PC; (ACC(15-0)) AND (dma) -> ACC(15-0); 0 -> ACC(31-16)

Operands: 0 <= dma <= 127; 0 <= n <= 7; ind: {* *+ *- *0+ *0- *BR0+ *BR0-}.

Opcode:

 direct:    0 1 1 0  1 1 1 0   0  <----- dma ----->      = 0x6E00
 indirect:  0 1 1 0  1 1 1 0   1  <- see Section 5.2      = 0x6E80

Toolchain base 0x6E00 agrees with the manual direct graphic for AND.

Status bits: None listed as affected for this form.

Words / Cycles: 1 word; 1 cycle for a DARAM operand (single execution).

Cycle class: see Instruction Timing.

Example:

    AND   *             ; ACC = 1234 5678h AND Data(*AR)(FF00h) = 0000 5600h

Bitwise AND of a long immediate constant (with shift) with the accumulator.

This is the long-immediate form of AND; see AND for the shared operation and status description.

Syntax: AND #lk [,shift]

Operation: (PC) + 2 -> PC; (ACC(30-0)) AND (lk x 2^shift) -> ACC. The constant is shifted left and zero-extended on both ends.

Operands: lk: 16-bit constant; 0 <= shift <= 16.

Opcode:

 15 14 13 12 | 11 10  9  8 |  7  6  5  4 |  3  2  1  0
  1  0  1  1 |  1  1  1  1 |  1  0  1  1 |  <-SHFT->      = 0xBFB0
 (second word = 16-bit constant)

Toolchain base 0xBFB0 agrees with the manual "long immediate with shift" graphic for AND.

Status bits: Not affected by SXM.

Words / Cycles: 2 words; 2 cycles (DARAM, single). Not repeatable.

Cycle class: see Instruction Timing.

Example:

    AND   #00FFh,4      ; ACC = 1234 5678h AND (00FFh << 4) = 0000 0670h

Add the shifted product register to the accumulator.

Syntax: APAC

Operation: (PC) + 1 -> PC; (ACC) + (shifted PREG) -> ACC

Operands: None.

Opcode:

 15 14 13 12 | 11 10  9  8 |  7  6  5  4 |  3  2  1  0
  1  0  1  1 |  1  1  1  0 |  0  0  0  0 |  0  1  0  0    = 0xBE04

Toolchain base 0xBE04 agrees with the manual graphic.

Status bits: Affected by OVM and PM; not affected by SXM; affects C and OV. PREG is shifted per the PM bits and is always sign-extended. APAC is a subset of LTA, LTD, MAC, MACD, MADS, MADD, MPYA, and SQRA.

Words / Cycles: 1 word; 1 cycle (DARAM, single).

Cycle class: I - see Instruction Timing.

Cycle timing (SPRU056D ch. 6):

Cycles for a Single Instruction:

Cycles for a Repeat (RPT) Execution:

Example:

    APAC                ; (PM = 01) ACC = 20h + (PREG 40h << 1) = A0h

AND a data-memory value with the DBMR or a long immediate constant, in place.

This is the general APL entry (a parallel logic unit instruction). The toolchain also exposes the forms as APLI (DBMR source, no long immediate) and APLK (long immediate specified); each has its own section below.

Syntax:

    Direct:     APL [#lk,] dma
    Indirect:   APL [#lk,] {ind} [,ARn]

Operation:

• Long immediate not specified: (PC) + 1 -> PC; (dma) AND (DBMR) -> dma
• Long immediate specified: (PC) + 2 -> PC; (dma) AND lk -> dma

The result is written back to the dma; the accumulator is unaffected.

Operands: 0 <= dma <= 127; lk: 16-bit constant; 0 <= n <= 7; ind: {* *+ *- *0+ *0- *BR0+ *BR0-}.

Opcode: The manual gives one graphic per form:

 direct, no long imm:     0 1 0 1  1 0 1 0   0  <----- dma ----->   = 0x5A00
 indirect, no long imm:   0 1 0 1  1 0 1 0   1  <- see Section 5.2  = 0x5A80
 direct, long imm:        0 1 0 1  1 1 1 0   0  <----- dma ----->   = 0x5E00
 indirect, long imm:      0 1 0 1  1 1 1 0   1  <- see Section 5.2  = 0x5E80
                          (long-immediate second word = 16-bit constant)

The toolchain stores 0x0003 as the base for the umbrella mnemonic APL; that value is a placeholder and does not match any single manual graphic, because the assembler resolves APL to one of the form-specific encodings above (also named APLI and APLK in the toolchain).

Status bits: Affects TC. The TC bit is set if the AND result is 0, otherwise cleared.

Words / Cycles: 1 word (no long immediate) or 2 words (long immediate specified); 1 cycle for a single DBMR-source DARAM execution, 2 cycles for the long-immediate form (DARAM).

Cycle class: V (APL); VI (APL) - see Instruction Timing.

Cycle timing (SPRU056D ch. 6):

Cycles for a Single Instruction (second operand DBMR):

• If the operand and the code are in the same SARAM block

Cycles for a Repeat (RPT) Execution (second operand DBMR):

• If the operand and the code are in the same SARAM block

Cycles for a Single Instruction (long immediate specified):

Cycles for a Repeat (RPT) Execution (long immediate specified):

• If the operand and the code reside in same SARAM block

Example:

    APL   DAT96         ; Data(60h) = 1111h AND DBMR(FF00h) = 1100h (DP = 0)
    APL   #0023h,DAT96  ; Data(60h) AND 0023h, in place (DP = 0)

AND a data-memory value with the DBMR, in place (no long immediate).

This is the DBMR-source form of APL; see APL for the shared operation and status description.

Syntax:

    Direct:     APL dma
    Indirect:   APL {ind} [,ARn]

Operation: (PC) + 1 -> PC; (dma) AND (DBMR) -> dma

Operands: 0 <= dma <= 127; 0 <= n <= 7; ind: {* *+ *- *0+ *0- *BR0+ *BR0-}.

Opcode:

 direct:    0 1 0 1  1 0 1 0   0  <----- dma ----->      = 0x5A00
 indirect:  0 1 0 1  1 0 1 0   1  <- see Section 5.2      = 0x5A80

Toolchain base 0x5A00 agrees with the manual "long immediate not specified" direct graphic for APL.

Status bits: Affects TC (set if the AND result is 0).

Words / Cycles: 1 word; 1 cycle for a single DBMR-source DARAM execution.

Cycle class: see Instruction Timing.

Example:

    APL   *,AR7         ; Data(*AR6)(0EFFh) AND DBMR(0303h) = 0203h, ARP -> 7

AND a long immediate constant with a data-memory value, in place.

This is the long-immediate form of APL; see APL for the shared operation and status description.

Syntax:

    Direct:     APL #lk, dma
    Indirect:   APL #lk, {ind} [,ARn]

Operation: (PC) + 2 -> PC; (dma) AND lk -> dma

Operands: 0 <= dma <= 127; lk: 16-bit constant; 0 <= n <= 7; ind: {* *+ *- *0+ *0- *BR0+ *BR0-}.

Opcode:

 direct:    0 1 0 1  1 1 1 0   0  <----- dma ----->      = 0x5E00
 indirect:  0 1 0 1  1 1 1 0   1  <- see Section 5.2      = 0x5E80
 (second word = 16-bit constant)

Toolchain base 0x5E00 agrees with the manual "long immediate specified" direct graphic for APL.

Status bits: Affects TC (set if the AND result is 0).

Words / Cycles: 2 words; 2 cycles (DARAM, single).

Cycle class: see Instruction Timing.

Example:

    APL   #0100h,*,AR6  ; Data(*AR5)(0FFFh) AND 0100h = 0100h, ARP -> 6

Several instructions on this page take one or more condition codes and transfer control only when the tested condition(s) hold. SPRU056D lists the conditions in the BCND entry as:

Not all combinations are meaningful, and testing BIO is mutually exclusive with testing TC. The exact TP and ZLVC field encodings for these conditions live in SPRU056D Table 6-1 (page 6-2), which is outside the provided source range; this page therefore does not decode those bit fields. See also the Program Control page.

The single-condition branch mnemonics BBNZ, BBZ, BC, BGEZ, BGZ, BIOZ, BLEZ, BLZ, BNC, BNV, BNZ, BV, and BZ are not given individual entries in the provided source range; SPRU056D documents their behavior through the general BCND entry. Each is a branch that tests exactly one condition. The condition named in each section below is the conventional meaning of the mnemonic; the base opcodes come from the toolchain table (source 2) and all share the BCND opcode-family prefix (bits 15-10 = 111000).

Unconditional branch to a program-memory address, with an optional AR/ARP update.

Syntax: B pma [, {ind} [,ARn ] ]

Operation: pma -> PC; modify current AR and ARP as specified.

Operands: 0 <= pma <= 65535; 0 <= n <= 7; ind: {* *+ *- *0+ *0- *BR0+ *BR0-}.

Opcode:

word 1:  15..8 = 0 1 1 1 1 0 0 1   bit7 = 1   bits6-0 = AR-update fields (see Section 5.2)
word 2:  16-bit pma constant
base: 0x7980   FMT 0x02

Status bits: None affected.

Words / Cycles: 2 words; 4 cycles (single execution, ROM/DARAM/SARAM). Not repeatable.

Cycle class: VIII - see Instruction Timing.

Cycle timing (SPRU056D ch. 6):

The B instruction is not repeatable.

Cycles for a Single Instruction:

[a] The 'C5x performs speculative fetching by reading two additional instruction words. If PC discontinuity is taken, these two instruction words are discarded.

Example: B 191,*+,AR1 - load 191 into the PC, increment the current AR, set ARP = 1.

Unconditional branch to the address held in the accumulator low word.

Syntax: BACC

Operation: ACC(15-0) -> PC.

Operands: None.

Opcode:

15..0 = 1 0 1 1 1 1 1 0  0 0 1 0 0 0 0 0
base: 0xBE20   FMT 0x00

Status bits: None affected.

Words / Cycles: 1 word; 4 cycles (single execution). Not repeatable.

Cycle class: X - see Instruction Timing.

Cycle timing (SPRU056D ch. 6):

The BACC instruction is not repeatable.

Cycles for a Single Instruction:

[a] The 'C5x performs speculative fetching by reading two additional instruction words. If PC discontinuity is taken, these two instruction words are discarded.

Example: BACC - with ACC = 191, continue execution from location 191.

Delayed branch to the address held in the accumulator low word; the following instruction word(s) execute before the branch is taken.

Syntax: BACCD

Operation: ACC(15-0) -> PC (after the delay slot executes).

Operands: None.

Opcode:

15..0 = 1 0 1 1 1 1 1 0  0 0 1 0 0 0 0 1
base: 0xBE21   FMT 0x00

Status bits: None affected.

Words / Cycles: 1 word; 2 cycles (single execution). Not repeatable.

Cycle class: XI - see Instruction Timing.

Cycle timing (SPRU056D ch. 6):

The BACCD instruction is not repeatable.

Cycles for a Single Instruction:

Example: BACCD then MAR *+,AR1 / LDP #5 - the two following words execute, then control passes to the ACC address.

Branch on auxiliary register not zero (loop control); the current AR is decremented by default.

Syntax: BANZ pma [, {ind} [,ARn ] ]

Operation: if (current AR) != 0: pma -> PC; else (PC) + 2 -> PC. Modify current AR as specified.

Operands: 0 <= pma <= 65535; 0 <= n <= 7; ind: {* *+ *- *0+ *0- *BR0+ *BR0-}.

Opcode:

word 1:  15..8 = 0 1 1 1 1 0 1 1   bit7 = 1   bits6-0 = AR-update fields (see Section 5.2)
word 2:  16-bit pma constant
base: 0x7B80   FMT 0x02

Status bits: None affected.

Words / Cycles: 2 words; 4 cycles if the branch is taken, 2 if not. Not repeatable.

Cycle class: VIII - see Instruction Timing.

Cycle timing (SPRU056D ch. 6):

The BANZ instruction is not repeatable.

Cycles for a Single Instruction:

[a] The 'C5x performs speculative fetching by reading two additional instruction words. If PC discontinuity is taken, these two instruction words are discarded.

Example: BANZ PGM191,AR0 - loop back to PGM191 while AR0 != 0, then fall through.

Delayed branch on auxiliary register not zero; the following instruction word(s) execute before the branch is taken.

Syntax: BANZD pma [, {ind} [,ARn ] ]

Operation: if (current AR) != 0: pma -> PC; else (PC) + 2 -> PC. Modify current AR as specified (after the delay slot).

Operands: 0 <= pma <= 65535; 0 <= n <= 7; ind: {* *+ *- *0+ *0- *BR0+ *BR0-}.

Opcode:

word 1:  15..8 = 0 1 1 1 1 1 1 1   bit7 = 1   bits6-0 = AR-update fields (see Section 5.2)
word 2:  16-bit pma constant
base: 0x7F80   FMT 0x02

Status bits: None affected.

Words / Cycles: 2 words; 2 cycles (single execution). Not repeatable.

Cycle class: IX - see Instruction Timing.

Cycle timing (SPRU056D ch. 6):

The BANZD instruction is not repeatable.

Cycles for a Single Instruction:

Example: BANZD PGM0 then LACC #01h / LDP #5 - the delay-slot words execute, then branch if the current AR is nonzero.

Branch if the TC (test/control) bit is set. Not individually documented in the source range; a single-condition form of BCND (see "About the condition codes").

Syntax: BBNZ pma (as a one-condition BCND; see BCND).

Operation: if (TC set): pma -> PC; else (PC) + 2 -> PC (as BCND).

Operands: 0 <= pma <= 65535 (as BCND).

Opcode:

base: 0xE100  (1110 0001 0000 0000)   FMT 0x02
word 2: 16-bit pma constant. Shares the BCND family prefix (bits 15-10 = 111000);
exact condition fields per Table 6-1 (page 6-2), outside the provided range.

Status bits: None affected (as BCND).

Words / Cycles: 2 words; 4 cycles if taken, 2 if not (as BCND). Not repeatable.

Cycle class: see Instruction Timing.

Example: BBNZ PGM191 - branch when TC = 1.

Branch if the TC (test/control) bit is cleared. Not individually documented in the source range; a single-condition form of BCND.

Syntax: BBZ pma (as a one-condition BCND; see BCND).

Operation: if (TC cleared): pma -> PC; else (PC) + 2 -> PC (as BCND).

Operands: 0 <= pma <= 65535 (as BCND).

Opcode:

base: 0xE200  (1110 0010 0000 0000)   FMT 0x02
word 2: 16-bit pma constant. Shares the BCND family prefix (bits 15-10 = 111000);
exact condition fields per Table 6-1 (page 6-2), outside the provided range.

Status bits: None affected (as BCND).

Words / Cycles: 2 words; 4 cycles if taken, 2 if not (as BCND). Not repeatable.

Cycle class: see Instruction Timing.

Example: BBZ PGM191 - branch when TC = 0.

Branch if carry: the C bit is set. Not individually documented in the source range; a single-condition form of BCND.

Syntax: BC pma (equivalent to BCND pma,C; see BCND).

Operation: if (C = 1): pma -> PC; else (PC) + 2 -> PC (as BCND).

Operands: 0 <= pma <= 65535 (as BCND).

Opcode:

base: 0xE311  (1110 0011 0001 0001)   FMT 0x02
word 2: 16-bit pma constant. Shares the BCND family prefix (bits 15-10 = 111000);
exact condition fields per Table 6-1 (page 6-2), outside the provided range.

Status bits: None affected (as BCND).

Words / Cycles: 2 words; 4 cycles if taken, 2 if not (as BCND). Not repeatable.

Cycle class: see Instruction Timing.

Example: BC PGM191 - branch when C = 1.

Conditional branch: transfer control to pma when the specified condition(s) are met.

Syntax: BCND pma, cond [,cond1 ] [,...]

Operation: if (condition(s)): pma -> PC; else (PC) + 2 -> PC.

Operands: 0 <= pma <= 65535; conditions as listed in "About the condition codes".

Opcode:

word 1:  15..10 = 1 1 1 0 0 0   bits9-8 = TP   bits7-4 = ZLVC   bits3-0 = ZLVC  (see Table 6-1)
word 2:  16-bit pma constant
base: 0xE300   FMT 0x18

Status bits: None affected.

Words / Cycles: 2 words; 4 cycles if the branch is taken, 2 if not. Not repeatable.

Cycle class: VIII - see Instruction Timing.

Cycle timing (SPRU056D ch. 6):

The BCND instruction is not repeatable.

Cycles for a Single Instruction:

[a] The 'C5x performs speculative fetching by reading two additional instruction words. If PC discontinuity is taken, these two instruction words are discarded.

Example: BCND PGM191,LEQ,C - branch to 191 if ACC <= 0 and C = 1.

Delayed conditional branch; the following instruction word(s) execute before the branch is taken and do not affect the tested conditions.

Syntax: BCNDD pma, cond [,cond1 ] [,...]

Operation: if (condition(s)): pma -> PC; else (PC) + 2 -> PC (after the delay slot).

Operands: 0 <= pma <= 65535; conditions as listed in "About the condition codes".

Opcode:

word 1:  15..10 = 1 1 1 1 0 0   bits9-8 = TP   bits7-4 = ZLVC   bits3-0 = ZLVC  (see Table 6-1)
word 2:  16-bit pma constant
base: 0xF300   FMT 0x18

Status bits: None affected.

Words / Cycles: 2 words; 2 cycles (single execution). Not repeatable.

Cycle class: IX - see Instruction Timing.

Cycle timing (SPRU056D ch. 6):

The BCNDD instruction is not repeatable.

Cycles for a Single Instruction:

Example: BCNDD PGM191,OV then MAR *,AR1 / LDP #5 - delay-slot words execute, then branch if OV is set.

Delayed unconditional branch; the following instruction word(s) execute before the branch is taken.

Syntax: BD pma [, {ind} [,ARn ] ]

Operation: pma -> PC; modify current AR and ARP as specified (after the delay slot).

Operands: 0 <= pma <= 65535; 0 <= n <= 7; ind: {* *+ *- *0+ *0- *BR0+ *BR0-}.

Opcode:

word 1:  15..8 = 0 1 1 1 1 1 0 1   bit7 = 1   bits6-0 = AR-update fields (see Section 5.2)
word 2:  16-bit pma constant
base: 0x7D80   FMT 0x02

Status bits: None affected.

Words / Cycles: 2 words; 2 cycles (single execution). Not repeatable.

Cycle class: IX - see Instruction Timing.

Cycle timing (SPRU056D ch. 6):

The BD instruction is not repeatable.

Cycles for a Single Instruction:

Example: BD 191 then MAR *+,AR1 / LDP #5 - delay-slot words execute, then control passes to 191.

Block move data-to-data, destination pointer in BMAR, direct addressing. Not a separate entry in the source range; this is the direct, destination-by-BMAR variant of BLDD (see BLDD). Its base opcode 0xAD00 matches the BLDD "DEST by BMAR, direct" encoding in the BLDD opcode graphic.

Syntax: BLDD dma, BMAR (this variant; see BLDD).

Operation: (dma) -> (dst addressed by BMAR); see BLDD for the full RPT sequence.

Operands: 0 <= dma <= 127.

Opcode:

15..8 = 1 0 1 0 1 1 0 1   bit7 = 0 (direct)   bits6-0 = dma
base: 0xAD00   FMT 0x01

Status bits: None affected (as BLDD).

Words / Cycles: 1 word; 2 cycles (single execution, representative; as BLDD with a BMAR pointer).

Cycle class: see Instruction Timing.

Example: BLDD 00h,BMAR - copy Data(dma) to the location addressed by BMAR.

Block move data-to-data, source pointer in BMAR, direct addressing. Not a separate entry in the source range; this is the direct, source-by-BMAR variant of BLDD (see BLDD). Its base opcode 0xAC00 matches the BLDD "SRC by BMAR, direct" encoding.

Syntax: BLDD BMAR, dma (this variant; see BLDD).

Operation: (src addressed by BMAR) -> (dma); see BLDD for the full RPT sequence.

Operands: 0 <= dma <= 127.

Opcode:

15..8 = 1 0 1 0 1 1 0 0   bit7 = 0 (direct)   bits6-0 = dma
base: 0xAC00   FMT 0x01

Status bits: None affected (as BLDD).

Words / Cycles: 1 word; 2 cycles (single execution, representative; as BLDD with a BMAR pointer).

Cycle class: see Instruction Timing.

Example: BLDD BMAR,20h - copy the BMAR-addressed word to Data(dma).

Branch if accumulator greater than or equal to zero (GEQ). Not individually documented in the source range; a single-condition form of BCND.

Syntax: BGEZ pma (equivalent to BCND pma,GEQ; see BCND).

Operation: if (ACC >= 0): pma -> PC; else (PC) + 2 -> PC (as BCND).

Operands: 0 <= pma <= 65535 (as BCND).

Opcode:

base: 0xE38C  (1110 0011 1000 1100)   FMT 0x02
word 2: 16-bit pma constant. Shares the BCND family prefix (bits 15-10 = 111000);
exact condition fields per Table 6-1 (page 6-2), outside the provided range.

Status bits: None affected (as BCND).

Words / Cycles: 2 words; 4 cycles if taken, 2 if not (as BCND). Not repeatable.

Cycle class: see Instruction Timing.

Example: BGEZ PGM191 - branch when ACC >= 0.

Branch if accumulator greater than zero (GT). Not individually documented in the source range; a single-condition form of BCND.

Syntax: BGZ pma (equivalent to BCND pma,GT; see BCND).

Operation: if (ACC > 0): pma -> PC; else (PC) + 2 -> PC (as BCND).

Operands: 0 <= pma <= 65535 (as BCND).

Opcode:

base: 0xE304  (1110 0011 0000 0100)   FMT 0x02
word 2: 16-bit pma constant. Shares the BCND family prefix (bits 15-10 = 111000);
exact condition fields per Table 6-1 (page 6-2), outside the provided range.

Status bits: None affected (as BCND).

Words / Cycles: 2 words; 4 cycles if taken, 2 if not (as BCND). Not repeatable.

Cycle class: see Instruction Timing.

Example: BGZ PGM191 - branch when ACC > 0.

Branch if the BIO pin is low. Not individually documented in the source range; a single-condition form of BCND (BIO condition).

Syntax: BIOZ pma (equivalent to BCND pma,BIO; see BCND).

Operation: if (BIO low): pma -> PC; else (PC) + 2 -> PC (as BCND).

Operands: 0 <= pma <= 65535 (as BCND).

Opcode:

base: 0xE000  (1110 0000 0000 0000)   FMT 0x02
word 2: 16-bit pma constant. Shares the BCND family prefix (bits 15-10 = 111000);
exact condition fields per Table 6-1 (page 6-2), outside the provided range.

Status bits: None affected (as BCND).

Words / Cycles: 2 words; 4 cycles if taken, 2 if not (as BCND). Not repeatable.

Cycle class: see Instruction Timing.

Example: BIOZ PGM191 - branch when the BIO pin is low.

Copy a fixed bit of a data-memory word to the TC status bit.

Syntax:

• Direct: BIT dma, bit code
• Indirect: BIT {ind} , bit code [,ARn ]

Operation: (PC) + 1 -> PC; (dma bit at bit address (15 - bit code)) -> TC.

Operands: 0 <= dma <= 127; 0 <= n <= 7; 0 <= bit code <= 15; ind: {* *+ *- *0+ *0- *BR0+ *BR0-}.

Opcode:

Direct:    15..12 = 0 1 0 0   bits11-8 = BITX (see Table 6-1)   bit7 = 0   bits6-0 = dma
Indirect:  15..12 = 0 1 0 0   bits11-8 = BITX                   bit7 = 1   bits6-0 = AR-update fields
base: 0x4000   FMT 0x0e

Status bits: Affects TC.

Words / Cycles: 1 word; 1 cycle (single execution, on-chip operand).

Cycle class: IIA - see Instruction Timing.

Cycle timing (SPRU056D ch. 6):

Cycles for a Single Instruction:

[a] If the operand and the code are in the same SARAM block

Cycles for a Repeat (RPT) Execution:

[a] If the operand and the code are in the same SARAM block

Example: BIT 0h,15 - copy the LSB of the addressed word into TC.

Copy a bit of a data-memory word, selected by the four LSBs of TREG2, to the TC status bit.

Syntax:

• Direct: BITT dma
• Indirect: BITT {ind} [,ARn ]

Operation: (PC) + 1 -> PC; (dma bit at bit address (15 - TREG2(3-0))) -> TC.

Operands: 0 <= dma <= 127; 0 <= n <= 7; ind: {* *+ *- *0+ *0- *BR0+ *BR0-}.

Opcode:

Direct:    15..8 = 0 1 1 0 1 1 1 1   bit7 = 0   bits6-0 = dma
Indirect:  15..8 = 0 1 1 0 1 1 1 1   bit7 = 1   bits6-0 = AR-update fields (see Section 5.2)
base: 0x6F00   FMT 0x01

Status bits: Affects TC.

Words / Cycles: 1 word; 1 cycle (single execution, on-chip operand).

Cycle class: IIA - see Instruction Timing.

Cycle timing (SPRU056D ch. 6):

Cycles for a Single Instruction:

[a] If the operand and the code are in the same SARAM block

Cycles for a Repeat (RPT) Execution:

[a] If the operand and the code are in the same SARAM block

Example: BITT 00h - test the bit of Data(dma) selected by TREG2(3-0) and copy it to TC.

Block move data-to-data, destination pointer by long immediate, direct addressing. Not a separate entry in the source range; this is the direct, destination-by-long-immediate variant of BLDD (see BLDD). Its base opcode 0xA900 matches the BLDD "DEST by long immediate, direct" encoding.

Syntax: BLDD dma, #addr (this variant; see BLDD).

Operation: (dma) -> (dst addressed by #addr); see BLDD for the full RPT sequence.

Operands: 0 <= dma <= 127; 0 <= addr <= 65535.

Opcode:

15..8 = 1 0 1 0 1 0 0 1   bit7 = 0 (direct)   bits6-0 = dma
word 2: 16-bit addr constant
base: 0xA900   FMT 0x11

Status bits: None affected (as BLDD).

Words / Cycles: 2 words; 3 cycles (single execution, representative; as BLDD with a long-immediate pointer).

Cycle class: see Instruction Timing.

Example: BLDD 00h,#321h - copy Data(dma) to data location 321h.

Block move within data memory: copy the word at the source dma to the destination dma. Source and/or destination may be pointed to by a long immediate value, by BMAR, or by a dma. Usable with RPT for multi-word moves.

Syntax (valid cases):

• BLDD BMAR, dma / BLDD BMAR, {ind} [,ARn ]
• BLDD dma, BMAR / BLDD {ind}, BMAR [,ARn ]
• BLDD #addr, dma / BLDD #addr, {ind} [,ARn ]
• BLDD dma, #addr / BLDD {ind}, #addr [,ARn ]

Operation: copy (src addressed by PFC) -> dst, iterated under the repeat counter; PFC sourced from BMAR or the long immediate; (PFC)+1 each pass; MCS save/restore around the move.

Operands: 0 <= addr <= 65535; 0 <= dma <= 127; 0 <= n <= 7; ind: {* *+ *- *0+ *0- *BR0+ *BR0-}.

Opcode:

SRC by BMAR:            15..8 = 1 0 1 0 1 1 0 0   bit7 = 0 direct (dma) / 1 indirect   -> 0xAC00 / 0xAC80
DEST by BMAR:           15..8 = 1 0 1 0 1 1 0 1   bit7 = 0 / 1                         -> 0xAD00 / 0xAD80
SRC by long immediate:  15..8 = 1 0 1 0 1 0 0 0   bit7 = 0 / 1   word2 = 16-bit const  -> 0xA800 / 0xA880
DEST by long immediate: 15..8 = 1 0 1 0 1 0 0 1   bit7 = 0 / 1   word2 = 16-bit const  -> 0xA900 / 0xA980
toolchain base: 0x0000   FMT 0x21

Opcode disagreement: the toolchain base 0x0000 (FMT 0x21) is a pseudo-base; it matches no encoding in the manual graphic. The real encodings above are carried by the FMT-0x21 expansion and by the toolchain's variant mnemonics BDSD (0xAC00), BDDD (0xAD00), BLKD (0xA800), and BKDK (0xA900).

Status bits: None affected.

Words / Cycles: 1 word when a pointer is BMAR, 2 words when a pointer is a long immediate; 2 cycles (BMAR form) or 3 cycles (long-immediate form), DARAM-to-DARAM single execution. With RPT it becomes effectively single-cycle per word once the pipeline is primed.

Cycle class: XIII (BLDD); XII (BLDD) - see Instruction Timing.

Cycle timing (SPRU056D ch. 6):

Cycles for a Single Instruction (SRC or DEST in BMAR):

[a] If the destination operand and the code are in the same SARAM block

Cycles for a Repeat (RPT) Execution (SRC or DEST in BMAR):

[a] If the destination operand and the code are in the same SARAM block [b] If both the source and the destination operands are in the same SARAM block [c] If both operands and the code are in the same SARAM block

Cycles for a Single Instruction (SRC or DEST long immediate):

[a] If the destination operand and the code are in the same SARAM block

Cycles for a Single Instruction (SRC or DEST long immediate) (Continued):

[a] If the destination operand and the code are in the same SARAM block

Cycles for a Repeat (RPT) Execution (SRC or DEST long immediate):

[a] If the destination operand and the code are in the same SARAM block [b] If both the source and the destination operands are in the same SARAM block [c] If both operands and the code are in the same SARAM block

Example: BLDD #300h,20h - copy data memory 300h into the dma 20h.

Block move from data memory to program memory; the destination pma is pointed to by BMAR. Usable with RPT.

Syntax:

• Direct: BLDP dma
• Indirect: BLDP {ind} [,ARn ]

Operation: (PC)+1 -> PC; (PFC) -> MCS; (BMAR) -> PFC; then copy (dma) -> (dst addressed by PFC), iterated under the repeat counter with (PFC)+1 each pass; (MCS) -> PFC.

Operands: 0 <= dma <= 127; 0 <= n <= 7; ind: {* *+ *- *0+ *0- *BR0+ *BR0-}.

Opcode:

Direct:    15..8 = 0 1 0 1 0 1 1 1   bit7 = 0   bits6-0 = dma
Indirect:  15..8 = 0 1 0 1 0 1 1 1   bit7 = 1   bits6-0 = AR-update fields (see Section 5.2)
base: 0x5700   FMT 0x01

Status bits: None affected.

Words / Cycles: 1 word; 2 cycles (single execution, DARAM-to-DARAM). Single-cycle per word under RPT once primed.

Cycle class: XVI - see Instruction Timing.

Cycle timing (SPRU056D ch. 6):

Cycles for a Single Instruction:

[a] If the destination operand and the code are in the same SARAM block [c] If both operands and the code are in the same SARAM block [d] If the source operand and the code are in the same SARAM block

Cycles for a Repeat (RPT) Execution:

[a] If the destination operand and the code are in the same SARAM block [b] If both the source and the destination operands are in the same SARAM block [c] If both operands and the code are in the same SARAM block [d] If the source operand and the code are in the same SARAM block

Cycles for a Repeat (RPT) Execution (Continued):

[a] If the destination operand and the code are in the same SARAM block [b] If both the source and the destination operands are in the same SARAM block [c] If both operands and the code are in the same SARAM block [d] If the source operand and the code are in the same SARAM block

Example: BLDP 00h - copy Data(dma) to the program location addressed by BMAR.

Branch if accumulator less than or equal to zero (LEQ). Not individually documented in the source range; a single-condition form of BCND.

Syntax: BLEZ pma (equivalent to BCND pma,LEQ; see BCND).

Operation: if (ACC <= 0): pma -> PC; else (PC) + 2 -> PC (as BCND).

Operands: 0 <= pma <= 65535 (as BCND).

Opcode:

base: 0xE3CC  (1110 0011 1100 1100)   FMT 0x02
word 2: 16-bit pma constant. Shares the BCND family prefix (bits 15-10 = 111000);
exact condition fields per Table 6-1 (page 6-2), outside the provided range.

Status bits: None affected (as BCND).

Words / Cycles: 2 words; 4 cycles if taken, 2 if not (as BCND). Not repeatable.

Cycle class: see Instruction Timing.

Example: BLEZ PGM191 - branch when ACC <= 0.

Block move data-to-data, source pointer by long immediate, direct addressing. Not a separate entry in the source range; this is the direct, source-by-long-immediate variant of BLDD (see BLDD). Its base opcode 0xA800 matches the BLDD "SRC by long immediate, direct" encoding.

Syntax: BLDD #addr, dma (this variant; see BLDD).

Operation: (src addressed by #addr) -> (dma); see BLDD for the full RPT sequence.

Operands: 0 <= dma <= 127; 0 <= addr <= 65535.

Opcode:

15..8 = 1 0 1 0 1 0 0 0   bit7 = 0 (direct)   bits6-0 = dma
word 2: 16-bit addr constant
base: 0xA800   FMT 0x11

Status bits: None affected (as BLDD).

Words / Cycles: 2 words; 3 cycles (single execution, representative; as BLDD with a long-immediate pointer).

Cycle class: see Instruction Timing.

Example: BLDD #300h,20h - copy data location 300h to the dma 20h.

Block move program-to-data, source pointer by long immediate, direct addressing. Not a separate entry in the source range; this is the direct, source-by-long-immediate variant of BLPD (see BLPD). Its base opcode 0xA500 matches the BLPD "SRC by long immediate, direct" encoding.

Syntax: BLPD #pma, dma (this variant; see BLPD).

Operation: (pma addressed by #pma) -> (dma); see BLPD for the full RPT sequence.

Operands: 0 <= pma <= 65535; 0 <= dma <= 127.

Opcode:

15..8 = 1 0 1 0 0 1 0 1   bit7 = 0 (direct)   bits6-0 = dma
word 2: 16-bit pma constant
base: 0xA500   FMT 0x11

Status bits: None affected (as BLPD).

Words / Cycles: 2 words; 3 cycles (single execution, representative; as BLPD with a long-immediate source).

Cycle class: see Instruction Timing.

Example: BLPD #800h,00h - copy program location 800h into the dma.

Block move from program memory to data memory. The source pma is pointed to by a long immediate value or by BMAR; the destination is a dma or the current AR. Usable with RPT.

Syntax (valid cases):

• BLPD BMAR, dma / BLPD BMAR, {ind} [,ARn ]
• BLPD #pma, dma / BLPD #pma, {ind} [,ARn ]

Operation: PFC sourced from the long immediate or BMAR (with (PFC) -> MCS saved first); copy (pma addressed by PFC) -> dst, iterated under the repeat counter with (PFC)+1 each pass; (MCS) -> PFC.

Operands: 0 <= pma <= 65535; 0 <= dma <= 127; 0 <= n <= 7; ind: {* *+ *- *0+ *0- *BR0+ *BR0-}.

Opcode:

SRC by BMAR:            15..8 = 1 0 1 0 0 1 0 0   bit7 = 0 direct (dma) / 1 indirect   -> 0xA400 / 0xA480
SRC by long immediate:  15..8 = 1 0 1 0 0 1 0 1   bit7 = 0 / 1   word2 = 16-bit const  -> 0xA500 / 0xA580
toolchain base: 0x0001   FMT 0x21

Opcode disagreement: the toolchain base 0x0001 (FMT 0x21) is a pseudo-base; it matches no encoding in the manual graphic. The real encodings above are carried by the FMT-0x21 expansion and by the toolchain's variant mnemonics BPSD (0xA400) and BLKP (0xA500).

Status bits: None affected.

Words / Cycles: 1 word when the source is BMAR, 2 words when the source is a long immediate; 2 cycles (BMAR form) or 3 cycles (long-immediate form), DARAM/ROM-to-DARAM single execution. Single-cycle per word under RPT once primed.

Cycle class: XV (BLPD); XIV (BLPD) - see Instruction Timing.

Cycle timing (SPRU056D ch. 6):

Cycles for a Single Instruction (SRC in BMAR):

[a] If the destination operand and the code are in the same SARAM block

Cycles for a Single Instruction (SRC in BMAR) (Continued):

[a] If the destination operand and the code are in the same SARAM block

Cycles for a Repeat (RPT) Execution (SRC in BMAR):

[a] If the destination operand and the code are in the same SARAM block [b] If both the source and the destination operands are in the same SARAM block [c] If both operands and the code are in the same SARAM block

Cycles for a Single Instruction (SRC long immediate):

[a] If the destination operand and the code are in the same SARAM block

Cycles for a Single Instruction (SRC long immediate) (Continued):

[a] If the destination operand and the code are in the same SARAM block

Cycles for a Repeat (RPT) Execution (SRC long immediate):

[a] If the destination operand and the code are in the same SARAM block [b] If both the source and the destination operands are in the same SARAM block [c] If both operands and the code are in the same SARAM block

Example: BLPD BMAR,00h - copy the BMAR-addressed program word into the dma.

Branch if accumulator less than zero (LT). Not individually documented in the source range; a single-condition form of BCND.

Syntax: BLZ pma (equivalent to BCND pma,LT; see BCND).

Operation: if (ACC < 0): pma -> PC; else (PC) + 2 -> PC (as BCND).

Operands: 0 <= pma <= 65535 (as BCND).

Opcode:

base: 0xE344  (1110 0011 0100 0100)   FMT 0x02
word 2: 16-bit pma constant. Shares the BCND family prefix (bits 15-10 = 111000);
exact condition fields per Table 6-1 (page 6-2), outside the provided range.

Status bits: None affected (as BCND).

Words / Cycles: 2 words; 4 cycles if taken, 2 if not (as BCND). Not repeatable.

Cycle class: see Instruction Timing.

Example: BLZ PGM191 - branch when ACC < 0.

Branch if no carry: the C bit is cleared. Not individually documented in the source range; a single-condition form of BCND.

Syntax: BNC pma (equivalent to BCND pma,NC; see BCND).

Operation: if (C = 0): pma -> PC; else (PC) + 2 -> PC (as BCND).

Operands: 0 <= pma <= 65535 (as BCND).

Opcode:

base: 0xE301  (1110 0011 0000 0001)   FMT 0x02
word 2: 16-bit pma constant. Shares the BCND family prefix (bits 15-10 = 111000);
exact condition fields per Table 6-1 (page 6-2), outside the provided range.

Status bits: None affected (as BCND).

Words / Cycles: 2 words; 4 cycles if taken, 2 if not (as BCND). Not repeatable.

Cycle class: see Instruction Timing.

Example: BNC PGM191 - branch when C = 0.

Branch if no overflow: the OV bit is cleared. Not individually documented in the source range; a single-condition form of BCND.

Syntax: BNV pma (equivalent to BCND pma,NOV; see BCND).

Operation: if (OV = 0): pma -> PC; else (PC) + 2 -> PC (as BCND).

Operands: 0 <= pma <= 65535 (as BCND).

Opcode:

base: 0xE302  (1110 0011 0000 0010)   FMT 0x02
word 2: 16-bit pma constant. Shares the BCND family prefix (bits 15-10 = 111000);
exact condition fields per Table 6-1 (page 6-2), outside the provided range.

Status bits: None affected (as BCND).

Words / Cycles: 2 words; 4 cycles if taken, 2 if not (as BCND). Not repeatable.

Cycle class: see Instruction Timing.

Example: BNV PGM191 - branch when OV = 0.

Branch if accumulator not zero (NEQ). Not individually documented in the source range; a single-condition form of BCND.

Syntax: BNZ pma (equivalent to BCND pma,NEQ; see BCND).

Operation: if (ACC != 0): pma -> PC; else (PC) + 2 -> PC (as BCND).

Operands: 0 <= pma <= 65535 (as BCND).

Opcode:

base: 0xE308  (1110 0011 0000 1000)   FMT 0x02
word 2: 16-bit pma constant. Shares the BCND family prefix (bits 15-10 = 111000);
exact condition fields per Table 6-1 (page 6-2), outside the provided range.

Status bits: None affected (as BCND).

Words / Cycles: 2 words; 4 cycles if taken, 2 if not (as BCND). Not repeatable.

Cycle class: see Instruction Timing.

Example: BNZ PGM191 - branch when ACC != 0.

Block move program-to-data, source pointer in BMAR, direct addressing. Not a separate entry in the source range; this is the direct, source-by-BMAR variant of BLPD (see BLPD). Its base opcode 0xA400 matches the BLPD "SRC by BMAR, direct" encoding.

Syntax: BLPD BMAR, dma (this variant; see BLPD).

Operation: (pma addressed by BMAR) -> (dma); see BLPD for the full RPT sequence.

Operands: 0 <= dma <= 127.

Opcode:

15..8 = 1 0 1 0 0 1 0 0   bit7 = 0 (direct)   bits6-0 = dma
base: 0xA400   FMT 0x01

Status bits: None affected (as BLPD).

Words / Cycles: 1 word; 2 cycles (single execution, representative; as BLPD with a BMAR source).

Cycle class: see Instruction Timing.

Example: BLPD BMAR,00h - copy the BMAR-addressed program word into the dma.

Barrel-shift the accumulator right by 1 to 16 bits in a single cycle.

Syntax: BSAR shift

Operation: (PC) + 1 -> PC; (ACC) / 2^shift -> ACC.

Operands: 1 <= shift <= 16.

Opcode:

15..8 = 1 0 1 1 1 1 1 1   bits7-4 = 1 1 1 0   bits3-0 = SHFT (see Table 6-1)
base: 0xBFE0   FMT 0x15

Status bits: Affected by SXM (SXM = 0 zero-fills the high bits; SXM = 1 sign-extends).

Words / Cycles: 1 word; 1 cycle (single execution).

Cycle class: I - see Instruction Timing.

Cycle timing (SPRU056D ch. 6):

Cycles for a Single Instruction:

Cycles for a Repeat (RPT) Execution:

Example: BSAR 4 - arithmetic right-shift the ACC by 4 bits.

Branch if overflow: the OV bit is set (and OV is then cleared by the test, per the overflow-flag semantics). Not individually documented in the source range; a single-condition form of BCND (OV condition).

Syntax: BV pma (equivalent to BCND pma,OV; see BCND).

Operation: if (OV = 1): pma -> PC; else (PC) + 2 -> PC (as BCND).

Operands: 0 <= pma <= 65535 (as BCND).

Opcode:

base: 0xE322  (1110 0011 0010 0010)   FMT 0x02
word 2: 16-bit pma constant. Shares the BCND family prefix (bits 15-10 = 111000);
exact condition fields per Table 6-1 (page 6-2), outside the provided range.

Status bits: None affected (as BCND).

Words / Cycles: 2 words; 4 cycles if taken, 2 if not (as BCND). Not repeatable.

Cycle class: see Instruction Timing.

Example: BV PGM191 - branch when OV = 1.

Branch if accumulator zero (EQ). Not individually documented in the source range; a single-condition form of BCND.

Syntax: BZ pma (equivalent to BCND pma,EQ; see BCND).

Operation: if (ACC = 0): pma -> PC; else (PC) + 2 -> PC (as BCND).

Operands: 0 <= pma <= 65535 (as BCND).

Opcode:

base: 0xE388  (1110 0011 1000 1000)   FMT 0x02
word 2: 16-bit pma constant. Shares the BCND family prefix (bits 15-10 = 111000);
exact condition fields per Table 6-1 (page 6-2), outside the provided range.

Status bits: None affected (as BCND).

Words / Cycles: 2 words; 4 cycles if taken, 2 if not (as BCND). Not repeatable.

Cycle class: see Instruction Timing.

Example: BZ PGM191 - branch when ACC = 0.

Computed call: push the return address and branch to the address in the accumulator low word.

Syntax: CALA

Operation: (PC) + 1 -> TOS; (ACC(15-0)) -> PC.

Operands: None.

Opcode:

15..0 = 1 0 1 1 1 1 1 0  0 0 1 1 0 0 0 0
base: 0xBE30   FMT 0x00

Status bits: None affected.

Words / Cycles: 1 word; 4 cycles (single execution). Not repeatable.

Cycle class: X - see Instruction Timing.

Cycle timing (SPRU056D ch. 6):

The CALA instruction is not repeatable.

Cycles for a Single Instruction:

[a] The 'C5x performs speculative fetching by reading two additional instruction words. If PC discontinuity is taken, these two instruction words are discarded.

Example: CALA - push PC+1, then continue at the ACC address.

Delayed computed call; the following instruction word(s) execute before the call is taken.

Syntax: CALAD

Operation: (PC) + 3 -> TOS; (ACC(15-0)) -> PC (after the delay slot).

Operands: None.

Opcode:

15..0 = 1 0 1 1 1 1 1 0  0 0 1 1 1 1 0 1
base: 0xBE3D   FMT 0x00

Status bits: None affected.

Words / Cycles: 1 word; 2 cycles (single execution). Not repeatable.

Cycle class: XI - see Instruction Timing.

Cycle timing (SPRU056D ch. 6):

The CALAD instruction is not repeatable.

Cycles for a Single Instruction:

Example: CALAD then MAR *+,AR1 / LDP #5 - delay-slot words execute, PC+3 is pushed, control passes to the ACC address.

Call a program-memory address: push the return address and branch, with an optional AR/ARP update.

Syntax: CALL pma [,{ind} [,ARn ] ]

Operation: (PC) + 2 -> TOS; pma -> PC; modify current AR and ARP as specified.

Operands: 0 <= pma <= 65535; 0 <= n <= 7; ind: {* *+ *- *0+ *0- *BR0+ *BR0-}.

Opcode:

word 1:  15..8 = 0 1 1 1 1 0 1 0   bit7 = 1   bits6-0 = AR-update fields (see Section 5.2)
word 2:  16-bit pma constant
base: 0x7A80   FMT 0x02

Status bits: None affected.

Words / Cycles: 2 words; 4 cycles (single execution). Not repeatable.

Cycle class: VIII - see Instruction Timing.

Cycle timing (SPRU056D ch. 6):

The CALL instruction is not repeatable.

Cycles for a Single Instruction:

[a] The 'C5x performs speculative fetching by reading two additional instruction words. If PC discontinuity is taken, these two instruction words are discarded.

Example: CALL PRG191,*+,AR0 - push the return address, branch to PRG191, increment the current AR, set ARP = 0.

Delayed call; the following instruction word(s) execute before the call is taken.

Syntax: CALLD pma [,{ind} [,ARn ] ]

Operation: (PC) + 4 -> TOS; pma -> PC; modify current AR and ARP as specified (after the delay slot).

Operands: 0 <= pma <= 65535; 0 <= n <= 7; ind: {* *+ *- *0+ *0- *BR0+ *BR0-}.

Opcode:

word 1:  15..8 = 0 1 1 1 1 1 1 0   bit7 = 1   bits6-0 = AR-update fields (see Section 5.2)
word 2:  16-bit pma constant
base: 0x7E80   FMT 0x02

Status bits: None affected.

Words / Cycles: 2 words; 2 cycles (single execution). Not repeatable.

Cycle class: IX - see Instruction Timing.

Cycle timing (SPRU056D ch. 6):

The CALLD instruction is not repeatable.

Cycles for a Single Instruction:

Example: CALLD PRG191 then MAR *+,AR1 / LDP #5 - delay-slot words execute, PC+4 is pushed, control passes to PRG191.

Conditional call: if the condition(s) are met, push the return address and branch to pma; behaves like CALL when all conditions are true.

Syntax: CC pma, cond [,cond1 ] [,...]

Operation: if (condition(s)): (PC) + 2 -> TOS, pma -> PC; else (PC) + 2 -> PC.

Operands: 0 <= pma <= 65535; conditions as listed in "About the condition codes". NTC, TC, and BIO are mutually exclusive.

Opcode:

word 1:  15..10 = 1 1 1 0 1 0   bits9-8 = TP   bits7-4 = ZLVC   bits3-0 = ZLVC  (see Table 6-1)
word 2:  16-bit pma constant
base: 0xEB00   FMT 0x18

Status bits: None affected.

Words / Cycles: 2 words; 4 cycles if the call is taken, 2 if not. Not repeatable.

Cycle class: VIII - see Instruction Timing.

Cycle timing (SPRU056D ch. 6):

The CC instruction is not repeatable.

Cycles for a Single Instruction:

[a] The 'C5x performs speculative fetching by reading two additional instruction words. If PC discontinuity is taken, these two instruction words are discarded.

Example: CC PGM191,LEQ,C - call PGM191 if ACC <= 0 and C = 1.

Delayed conditional call; the following instruction word(s) execute before the call is taken. Behaves like CALLD when all conditions are true.

Syntax: CCD pma, cond [,cond1 ] [,...]

Operation: if (condition(s)): (PC) + 4 -> TOS, pma -> PC; else (PC) + 2 -> PC (after the delay slot).

Operands: 0 <= pma <= 65535; conditions as listed in "About the condition codes". NTC, TC, and BIO are mutually exclusive.

Opcode:

word 1:  15..10 = 1 1 1 1 1 0   bits9-8 = TP   bits7-4 = ZLVC   bits3-0 = ZLVC  (see Table 6-1)
word 2:  16-bit pma constant
base: 0xFB00   FMT 0x18

Status bits: None affected.

Words / Cycles: 2 words; 2 cycles (single execution). Not repeatable.

Cycle class: IX - see Instruction Timing.

Cycle timing (SPRU056D ch. 6):

The CCD instruction is not repeatable.

Cycles for a Single Instruction:

Example: CCD PGM191,LEQ,C then MAR *+,AR1 / LDP #5 - delay-slot words execute, then the conditional call is taken.

Clear a single CPU control/status bit.

Syntax: CLRC control bit

Operation: (PC) + 1 -> PC; 0 -> control bit.

Operands: control bit: {C, CNF, HM, INTM, OVM, SXM, TC, XF}.

Opcode:

Common field 15..6 = 1 0 1 1 1 1 1 0 0 1, bit5 = 0; bits4-0 select the control bit:
  INTM -> 0xBE40   OVM -> 0xBE42   CNF -> 0xBE44   SXM -> 0xBE46
  HM   -> 0xBE48   TC  -> 0xBE4A   XF  -> 0xBE4C   C   -> 0xBE4E
toolchain base: 0x0000   FMT 0x22

Opcode disagreement: the toolchain base 0x0000 (FMT 0x22) is a pseudo-base; it matches no encoding in the manual graphic. The real per-bit encodings form the 0xBE40..0xBE4E family shown above (derived from the CLRC opcode graphics in the source range). Note that CLRC CNF (0xBE44) coincides with the CNFD instruction.

Status bits: Affects the selected control bit.

Words / Cycles: 1 word; 1 cycle (single execution).

Cycle class: I - see Instruction Timing.

Cycle timing (SPRU056D ch. 6):

Cycles for a Single Instruction:

Cycles for a Repeat (RPT) Execution:

Example: CLRC TC - clear the TC bit (bit 11 of ST1).

Complement the accumulator (ones complement).

Syntax: CMPL

Operation: (PC) + 1 -> PC; (ACC inverted) -> ACC.

Operands: None.

Opcode:

15..0 = 1 0 1 1 1 1 1 0  0 0 0 0 0 0 0 1
base: 0xBE01   FMT 0x00

Status bits: Does not affect C.

Words / Cycles: 1 word; 1 cycle (single execution).

Cycle class: I - see Instruction Timing.

Cycle timing (SPRU056D ch. 6):

Cycles for a Single Instruction:

Cycles for a Repeat (RPT) Execution:

Example: CMPL - replace the ACC with its logical inversion.

Compare the current auxiliary register against the auxiliary register compare register (ARCR) and set TC to the result.

Syntax: CMPR CM

Operation: (PC) + 1 -> PC; compare (current AR) to (ARCR); set TC = 1 if the CM-selected relation holds, else 0.

Operands: 0 <= CM <= 3. CM = 00: AR = ARCR; 01: AR < ARCR; 10: AR > ARCR; 11: AR != ARCR. ARs are compared as unsigned integers.

Opcode:

15..8 = 1 0 1 1 1 1 1 1   bits7-2 = 0 1 0 0 0 1   bits1-0 = CM (see Table 6-1)
base: 0xBF44   FMT 0x0c

Status bits: Affected by NDX; not affected by SXM; affects TC; does not affect SXM.

Words / Cycles: 1 word; 1 cycle (single execution).

Cycle class: I - see Instruction Timing.

Cycle timing (SPRU056D ch. 6):

Cycles for a Single Instruction:

Cycles for a Repeat (RPT) Execution:

Example: CMPR 2 - set TC if the current AR > ARCR.

Configure the on-chip RAM block as data memory (clear the CNF bit). Not given a separate entry in the provided source range. Its opcode 0xBE44 is identical to the CLRC CNF encoding derived from the in-range CLRC graphics, which corroborates the toolchain value.

Syntax: CNFD (no operands; equivalent to CLRC CNF).

Operation: not detailed in the source range (clears the CNF configuration bit; see CLRC).

Operands: None.

Opcode:

15..0 = 1 0 1 1 1 1 1 0  0 1 0 0 0 1 0 0
base: 0xBE44   FMT 0x00

Status bits: Affects the CNF control bit (as CLRC CNF); otherwise not specified in the source range.

Words / Cycles: 1 word; cycle count not specified in the source range (CLRC-class control instruction: 1 cycle single execution).

Cycle class: see Instruction Timing.

Example: CNFD - configure the reconfigurable RAM block as data memory.

Configure the on-chip RAM block as program memory (set the CNF bit). Not given a separate entry in the provided source range. Its opcode 0xBE45 is the companion (CNF-set) encoding one above CNFD (0xBE44 = CLRC CNF); the set form (SETC CNF) is outside the B-C range.

Syntax: CNFP (no operands; companion of SETC CNF).

Operation: not detailed in the source range (sets the CNF configuration bit).

Operands: None.

Opcode:

15..0 = 1 0 1 1 1 1 1 0  0 1 0 0 0 1 0 1
base: 0xBE45   FMT 0x00

Status bits: Affects the CNF control bit; otherwise not specified in the source range.

Words / Cycles: 1 word; cycle count not specified in the source range.

Cycle class: see Instruction Timing.

Example: CNFP - configure the reconfigurable RAM block as program memory.

Configure on-chip RAM block(s) via a 2-bit operand. Not documented in the provided source range.

Syntax: not specified in the source range (takes a block-configuration operand).

Operation: not specified in the source range.

Operands: not specified in the source range.

Opcode:

toolchain base: 0x0000   FMT 0x0c

Opcode disagreement / unverifiable: the toolchain base 0x0000 (FMT 0x0c) is a pseudo-base and matches no encoding available in the provided source range, which does not contain a CONF entry. The true encoding could not be verified here.

Status bits: not specified in the source range.

Words / Cycles: not specified in the source range.

Cycle class: see Instruction Timing.

Example: not specified in the source range.

Compare a data-memory word against a long immediate constant or against the dynamic bit manipulation register (DBMR), and set TC to the result.

Syntax:

• Direct: CPL [,#lk ] dma
• Indirect: CPL [,#lk ] {ind} [,ARn ]

Operation: long immediate not specified: (PC)+1 -> PC, compare (DBMR) to (dma), TC = 1 if equal else 0. Long immediate specified: (PC)+2 -> PC, compare lk to (dma), TC = 1 if equal else 0.

Operands: 0 <= dma <= 127; lk: 16-bit constant; 0 <= n <= 7; ind: {* *+ *- *0+ *0- *BR0+ *BR0-}.

Opcode:

Long immediate NOT specified:  15..8 = 0 1 0 1 1 0 1 1   bit7 = 0 direct (dma) / 1 indirect  -> 0x5B00 / 0x5B80
Long immediate specified:      15..8 = 0 1 0 1 1 1 1 1   bit7 = 0 / 1   word2 = 16-bit lk    -> 0x5F00 / 0x5F80
toolchain base: 0x0006   FMT 0x1e

Opcode disagreement: the toolchain base 0x0006 (FMT 0x1e) is a pseudo-base; it matches no encoding in the manual graphic. The real encodings above are carried by the FMT-0x1e expansion and by the toolchain's variant mnemonics CPLI (0x5B00, DBMR compare) and CPLK (0x5F00, long-immediate compare).

Status bits: Not affected by SXM; affects TC.

Words / Cycles: 1 word (long immediate not specified) or 2 words (specified); 1 cycle (no long immediate) or 2 cycles (long immediate), single execution with an on-chip operand.

Cycle class: IIA (CPL); VIIa (CPL #lk) - see Instruction Timing.

Cycle timing (SPRU056D ch. 6):

Cycles for a Single Instruction:

[a] If the operand and the code are in the same SARAM block

Cycles for a Repeat (RPT) Execution:

[a] If the operand and the code are in the same SARAM block

Cycles for a Single Instruction (long immediate specified):

[a] If the operand and the code are in the same SARAM block

Cycles for a Repeat (RPT) Execution (long immediate specified):

[a] If the operand and the code are in the same SARAM block

Example: CPL #060h,60h - compare the constant 060h against Data(60h) and set TC.

Compare a data-memory word against the DBMR (long immediate not specified), direct addressing. Not a separate entry in the source range; this is the direct, no-long-immediate variant of CPL (see CPL). Its base opcode 0x5B00 matches the CPL "long immediate not specified, direct" encoding.

Syntax: CPL dma (this variant; see CPL).

Operation: (PC)+1 -> PC; compare (DBMR) to (dma); TC = 1 if equal else 0.

Operands: 0 <= dma <= 127.

Opcode:

15..8 = 0 1 0 1 1 0 1 1   bit7 = 0 (direct)   bits6-0 = dma
base: 0x5B00   FMT 0x01

Status bits: Not affected by SXM; affects TC (as CPL).

Words / Cycles: 1 word; 1 cycle (single execution, on-chip operand).

Cycle class: see Instruction Timing.

Example: CPL 60h - compare Data(60h) against the DBMR and set TC.

Compare a data-memory word against a 16-bit long immediate constant, direct addressing. Not a separate entry in the source range; this is the direct, long-immediate variant of CPL (see CPL). Its base opcode 0x5F00 matches the CPL "long immediate specified, direct" encoding.

Syntax: CPL #lk, dma (this variant; see CPL).

Operation: (PC)+2 -> PC; compare lk to (dma); TC = 1 if equal else 0.

Operands: 0 <= dma <= 127; lk: 16-bit constant.

Opcode:

15..8 = 0 1 0 1 1 1 1 1   bit7 = 0 (direct)   bits6-0 = dma
word 2: 16-bit lk constant
base: 0x5F00   FMT 0x14

Status bits: Not affected by SXM; affects TC (as CPL).

Words / Cycles: 2 words; 2 cycles (single execution, on-chip operand).

Cycle class: see Instruction Timing.

Example: CPL #060h,60h - compare 060h against Data(60h) and set TC.

Load the signed maximum of the accumulator and the accumulator buffer into both, and set the carry accordingly.

Syntax: CRGT

Operation: (PC) + 1 -> PC; compare (ACC) to (ACCB). If ACC > ACCB: ACC -> ACCB, 1 -> C. If ACC < ACCB: ACCB -> ACC, 0 -> C. If ACC = ACCB: 1 -> C.

Operands: None.

Opcode:

15..0 = 1 0 1 1 1 1 1 0  0 0 0 1 1 0 1 1
base: 0xBE1B   FMT 0x00

Status bits: Affects C (set when ACC >= ACCB, else cleared).

Words / Cycles: 1 word; 1 cycle (single execution).

Cycle class: I - see Instruction Timing.

Cycle timing (SPRU056D ch. 6):

Cycles for a Single Instruction:

Cycles for a Repeat (RPT) Execution:

Example: CRGT - with ACC = 5h and ACCB = 4h, both become 5h and C is set.

Load the signed minimum of the accumulator and the accumulator buffer into both, and set the carry accordingly.

Syntax: CRLT

Operation: (PC) + 1 -> PC; compare (ACC) to (ACCB). If ACC < ACCB: ACC -> ACCB, 1 -> C. If ACC > ACCB: ACCB -> ACC, 0 -> C. If ACC = ACCB: 0 -> C.

Operands: None.

Opcode:

15..0 = 1 0 1 1 1 1 1 0  0 0 0 1 1 1 0 0
base: 0xBE1C   FMT 0x00

Status bits: Affects C (set when ACC < ACCB, else cleared).

Words / Cycles: 1 word; 1 cycle (single execution).

Cycle class: I - see Instruction Timing.

Cycle timing (SPRU056D ch. 6):

Cycles for a Single Instruction:

Cycles for a Repeat (RPT) Execution:

Example: CRLT - with ACC = 4h and ACCB = 5h, both become 4h and C is set.

Description: Disable-interrupt mnemonic. Not documented within the provided source range (SPRU056D chapter 6, lines 12363-14217); listed here from the toolchain opcode table for completeness.

Syntax: not specified (outside source range)

Operation: not specified (outside source range)

Operands: not specified (outside source range)

Opcode: ASCII field row not specified (outside source range); base hex 0xBE41 (sl_DL.txt). Not cross-checkable against the source range.

Status bits: not specified (outside source range)

Words / Cycles: not specified (outside source range)

Cycle class: see Instruction Timing.

Example: not specified (outside source range)

Description: Copies a data-memory word up to the next-higher address, implementing the single-sample delay used by digital filters.

Syntax: DMOV dma (direct); DMOV {ind} [,ARn] (indirect)

Operation: (PC) + 1 -> PC; (dma) -> dma + 1

Operands: 0 <= dma <= 127; 0 <= n <= 7; ind in {* *+ *- *0+ *0- *BR0+ *BR0-}

Opcode: Direct 0111 0111 0 ddddddd; Indirect 0111 0111 1 .... Base hex 0x7700 (sl_DL.txt), matches the manual direct row.

Status bits: Affected by CNF and OVLY.

Words / Cycles: Words 1; Cycles 1 (single, operand in DARAM). Works only in on-chip data RAM; on external memory or memory-mapped registers it reads but performs no move.

Cycle class: V - see Instruction Timing.

Cycle timing (SPRU056D ch. 6):

Cycles for a Single Instruction

• If the operand and the code are in the same SARAM block

Cycles for a Repeat (RPT) Execution

• If the operand and the code are in the same SARAM block

Example: DMOV DAT8 copies Data(308h) into Data(309h), leaving 308h unchanged.

Description: Emulation opcode (toolchain mnemonic EHWBS). Not documented within the provided source range; listed from the toolchain opcode table for completeness.

Syntax: not specified (outside source range)

Operation: not specified (outside source range)

Operands: not specified (outside source range)

Opcode: ASCII field row not specified (outside source range); base hex 0xBEB1 (sl_DL.txt). Not cross-checkable against the source range.

Status bits: not specified (outside source range)

Words / Cycles: not specified (outside source range)

Cycle class: see Instruction Timing.

Example: not specified (outside source range)

Description: Emulation opcode (toolchain mnemonic EHWBT). Not documented within the provided source range; listed from the toolchain opcode table for completeness.

Syntax: not specified (outside source range)

Operation: not specified (outside source range)

Operands: not specified (outside source range)

Opcode: ASCII field row not specified (outside source range); base hex 0xBEB3 (sl_DL.txt). Not cross-checkable against the source range.

Status bits: not specified (outside source range)

Words / Cycles: not specified (outside source range)

Cycle class: see Instruction Timing.

Example: not specified (outside source range)

Description: Enable-interrupt mnemonic. Not documented within the provided source range; listed from the toolchain opcode table for completeness.

Syntax: not specified (outside source range)

Operation: not specified (outside source range)

Operands: not specified (outside source range)

Opcode: ASCII field row not specified (outside source range); base hex 0xBE40 (sl_DL.txt). Not cross-checkable against the source range.

Status bits: not specified (outside source range)

Words / Cycles: not specified (outside source range)

Cycle class: see Instruction Timing.

Example: not specified (outside source range)

Description: Emulation opcode (toolchain mnemonic EMPSD). Not documented within the provided source range; listed from the toolchain opcode table for completeness.

Syntax: not specified (outside source range)

Operation: not specified (outside source range)

Operands: not specified (outside source range)

Opcode: ASCII field row not specified (outside source range); base hex 0xBEB0 (sl_DL.txt). Not cross-checkable against the source range.

Status bits: not specified (outside source range)

Words / Cycles: not specified (outside source range)

Cycle class: see Instruction Timing.

Example: not specified (outside source range)

Description: Emulation opcode (toolchain mnemonic EMRET). Not documented within the provided source range; listed from the toolchain opcode table for completeness.

Syntax: not specified (outside source range)

Operation: not specified (outside source range)

Operands: not specified (outside source range)

Opcode: ASCII field row not specified (outside source range); base hex 0xBE92 (sl_DL.txt). Not cross-checkable against the source range.

Status bits: not specified (outside source range)

Words / Cycles: not specified (outside source range)

Cycle class: see Instruction Timing.

Example: not specified (outside source range)

Description: Emulation opcode (toolchain mnemonic ESTOP). Not documented within the provided source range; listed from the toolchain opcode table for completeness.

Syntax: not specified (outside source range)

Operation: not specified (outside source range)

Operands: not specified (outside source range)

Opcode: ASCII field row not specified (outside source range); base hex 0xBE90 (sl_DL.txt). Not cross-checkable against the source range.

Status bits: not specified (outside source range)

Words / Cycles: not specified (outside source range)

Cycle class: see Instruction Timing.

Example: not specified (outside source range)

Description: Emulation opcode (toolchain mnemonic ESTPD). Not documented within the provided source range; listed from the toolchain opcode table for completeness.

Syntax: not specified (outside source range)

Operation: not specified (outside source range)

Operands: not specified (outside source range)

Opcode: ASCII field row not specified (outside source range); base hex 0xBE91 (sl_DL.txt). Not cross-checkable against the source range.

Status bits: not specified (outside source range)

Words / Cycles: not specified (outside source range)

Cycle class: see Instruction Timing.

Example: not specified (outside source range)

Description: Emulation opcode (toolchain mnemonic ETRAP). Not documented within the provided source range; listed from the toolchain opcode table for completeness.

Syntax: not specified (outside source range)

Operation: not specified (outside source range)

Operands: not specified (outside source range)

Opcode: ASCII field row not specified (outside source range); base hex 0xBE93 (sl_DL.txt). Not cross-checkable against the source range.

Status bits: not specified (outside source range)

Words / Cycles: not specified (outside source range)

Cycle class: see Instruction Timing.

Example: not specified (outside source range)

Description: Swaps the accumulator with the accumulator buffer in a single cycle.

Syntax: EXAR

Operation: (PC) + 1 -> PC; (ACCB) <-> (ACC)

Operands: none

Opcode: 1011 1110 0001 1101. Base hex 0xBE1D (sl_DL.txt), matches the manual row.

Status bits: none affected.

Words / Cycles: Words 1; Cycles 1 (single).

Cycle class: I - see Instruction Timing.

Cycle timing (SPRU056D ch. 6):

Cycles for a Single Instruction

Cycles for a Repeat (RPT) Execution

Example: EXAR with ACC = 043h and ACCB = 02h leaves ACC = 02h and ACCB = 043h.

Description: Toolchain mnemonic FORT. Not documented within the provided source range; listed from the toolchain opcode table for completeness.

Syntax: not specified (outside source range)

Operation: not specified (outside source range)

Operands: not specified (outside source range)

Opcode: ASCII field row not specified (outside source range); base hex 0x0000 (sl_DL.txt, format code 0x0D). The 0x0000 value looks like a format seed rather than a literal opcode and cannot be verified against the source range.

Status bits: not specified (outside source range)

Words / Cycles: not specified (outside source range)

Cycle class: see Instruction Timing.

Example: not specified (outside source range)

Description: Halts the processor in power-down mode until an unmasked interrupt or reset occurs.

Syntax: IDLE

Operation: (PC) + 1 -> PC

Operands: none

Opcode: 1011 1110 0010 0010. Base hex 0xBE22 (sl_DL.txt), matches the manual row.

Status bits: Affected by INTM. With INTM set, execution resumes after IDLE; with INTM cleared, control branches to the interrupt service routine.

Words / Cycles: Words 1; Cycles 1 (single). Not repeatable. Timer and serial-port peripherals stay active during idle.

Cycle class: I - see Instruction Timing.

Cycle timing (SPRU056D ch. 6):

The IDLE instruction is not repeatable.

Cycles for a Single Instruction

Example: IDLE parks the processor until a reset or unmasked interrupt arrives.

Description: Alternate mnemonic for IDLE; the toolchain table assigns it the same encoding as IDLE.

Syntax: IDLE1

Operation: Same as IDLE (shared opcode): (PC) + 1 -> PC

Operands: none

Opcode: 1011 1110 0010 0010. Base hex 0xBE22 (sl_DL.txt), identical to IDLE.

Status bits: Same as IDLE (shared opcode): affected by INTM.

Words / Cycles: Words 1; Cycles 1 (single). Not repeatable.

Cycle class: see Instruction Timing.

Example: IDLE1 behaves as IDLE, parking the processor until an unmasked interrupt or reset.

Description: Enters a deeper power-down than IDLE by removing the functional clock, waiting for an unmasked interrupt or reset.

Syntax: IDLE2

Operation: (PC) + 1 -> PC

Operands: none

Opcode: 1011 1110 0010 0011. Base hex 0xBE23 (sl_DL.txt), matches the manual row.

Status bits: Affected by INTM.

Words / Cycles: Words 1; Cycles 1 (single). Not repeatable. Timer and serial-port peripherals are inactive; exit needs a low level of at least five machine cycles on an external interrupt, RS, or NMI.

Cycle class: I - see Instruction Timing.

Cycle timing (SPRU056D ch. 6):

The IDLE2 instruction is not repeatable.

Cycles for a Single Instruction

Example: IDLE2 parks the processor in low-power mode until a reset or unmasked external interrupt.

Description: Reads a 16-bit word from an I/O port into data memory.

Syntax: IN dma, PA (direct); IN {ind}, PA [,ARn] (indirect)

Operation: (PC) + 2 -> PC; port address -> address bus; data bus -> dma; port address + 1 -> port address (per repeat)

Operands: 0 <= dma <= 127; 0 <= n <= 7; 0 <= PA <= 65535; ind in {* *+ *- *0+ *0- *BR0+ *BR0-}

Opcode: Direct 1010 1111 0 ddddddd then a 16-bit port constant word; Indirect 1010 1111 1 ... then the 16-bit port constant. Base hex 0xAF00 (sl_DL.txt), matches the manual direct row.

Status bits: none affected.

Words / Cycles: Words 2; Cycles 2 + iosrc (single, destination in DARAM). With RPT the port address auto-increments and the body runs in one cycle once the pipeline is primed.

Cycle class: XXVI - see Instruction Timing.

Cycle timing (SPRU056D ch. 6):

Cycles for a Single Instruction

• If the destination operand and the code are in the same SARAM block

Cycles for a Repeat (RPT) Execution

• If the destination operand and the code are in the same SARAM block

Example: IN DAT7,PA5 reads I/O port 55h into data memory location 307h (DP = 6).

Description: Software interrupt that vectors to a selected interrupt location, pushing the return address.

Syntax: INTR K

Operation: (PC) + 1 -> stack; corresponding interrupt vector -> PC

Operands: 0 <= K <= 31

Opcode: 1011 1110 0 11 kkkkk (K in the INTR# field). Base hex 0xBE60 (sl_DL.txt), matches the manual row.

Status bits: Not affected by INTM; affects INTM. The INTR vector does not clear the matching IFR bit.

Words / Cycles: Words 1; Cycles 4 (single). Not repeatable.

Cycle class: X - see Instruction Timing.

Cycle timing (SPRU056D ch. 6):

The INTR instruction is not repeatable.

Cycles for a Single Instruction

• The 'C5x performs speculative fetching by reading two additional instruction words. If PC discontinuity is taken, these two instruction words are discarded.

Example: INTR 3 passes control to program-memory location 6h and pushes PC + 1.

Description: Earlier mnemonic for LACC (load accumulator with left shift); the toolchain table gives LAC and LACC the same encoding.

Syntax: LAC dma [,shift] (direct); LAC {ind} [,shift [,ARn]] (indirect); LAC #lk [,shift] (long immediate)

Operation: Same as LACC (shared opcode): shifted (dma) or shifted lk -> ACC

Operands: 0 <= dma <= 127; 0 <= n <= 7; 0 <= shift <= 16; -32768 <= lk <= 32767; ind in {* *+ *- *0+ *0- *BR0+ *BR0-}

Opcode: Same bit rows as LACC. Direct with shift 0001 ssss 0 ddddddd (base 0x1000). sl_DL.txt lists LAC as 0x0001, a toolchain format seed that does not equal the 0x1000 direct-with-shift base; see the LACC and LACI sections.

Status bits: Same as LACC (shared opcode): affected by SXM.

Words / Cycles: Words 1 (direct/indirect) or 2 (long immediate); Cycles 1 (single, direct/indirect, operand in DARAM).

Cycle class: see Instruction Timing.

Example: LAC DAT6,4 loads Data(dma) left-shifted by 4 into ACC.

Description: Loads the accumulator from the accumulator buffer.

Syntax: LACB

Operation: (PC) + 1 -> PC; (ACCB) -> ACC

Operands: none

Opcode: 1011 1110 0001 1111. Base hex 0xBE1F (sl_DL.txt), matches the manual row.

Status bits: none affected.

Words / Cycles: Words 1; Cycles 1 (single).

Cycle class: I - see Instruction Timing.

Cycle timing (SPRU056D ch. 6):

Cycles for a Single Instruction

Cycles for a Repeat (RPT) Execution

Example: LACB copies ACCB (5555 AAAAh) into ACC.

Description: Loads the accumulator with a data-memory word or 16-bit constant, left-shifted by a shift code.

Syntax: LACC dma [,shift] (direct); LACC {ind} [,shift [,ARn]] (indirect); LACC #lk [,shift] (long immediate)

Operation: Direct/indirect: (dma) x 2^shift -> ACC. Long immediate: lk x 2^shift -> ACC. Low bits zero-filled; high bits sign-extended if SXM set, else zero-filled.

Operands: 0 <= dma <= 127; 0 <= n <= 7; 0 <= shift <= 16 (default 0); -32768 <= lk <= 32767; ind in {* *+ *- *0+ *0- *BR0+ *BR0-}

Opcode: Direct with shift 0001 ssss 0 ddddddd (base 0x1000); Indirect with shift 0001 ssss 1 ...; Direct with shift of 16 0110 1010 0 ddddddd (0x6A00); Indirect with shift of 16 0110 1010 1 ...; Long immediate with shift 1011 1111 1000 ssss then 16-bit constant (0xBF80). sl_DL.txt lists LACC as 0x0001, a format seed; the real direct-with-shift base 0x1000 is carried in the toolchain table under LACI.

Status bits: Affected by SXM.

Words / Cycles: Words 1 (direct/indirect) or 2 (long immediate); Cycles 1 (single, direct/indirect, operand in DARAM); long immediate is not repeatable.

Cycle class: IIA (LACC); III (LACC #lk) - see Instruction Timing.

Cycle timing (SPRU056D ch. 6):

For the long immediate addressing modes, the LACC instruction is not repeatable.

Cycles for a Single Instruction (direct or indirect addressing)

• If the operand and the code are in the same SARAM block

Cycles for a Repeat (RPT) Execution (direct or indirect addressing)

• If the operand and the code are in the same SARAM block

Cycles for a Single Instruction (long immediate addressing)

Example: LACC #F000h,1 with SXM = 1 loads FFFF E000h into ACC.

Description: Toolchain-internal name for the concrete direct/indirect-with-shift encoding of LACC.

Syntax: LACI dma [,shift] (direct); LACI {ind} [,shift [,ARn]] (indirect)

Operation: Same as LACC direct/indirect (shared encoding): (dma) x 2^shift -> ACC

Operands: 0 <= dma <= 127; 0 <= n <= 7; 0 <= shift <= 16; ind in {* *+ *- *0+ *0- *BR0+ *BR0-}

Opcode: Direct with shift 0001 ssss 0 ddddddd; Indirect with shift 0001 ssss 1 .... Base hex 0x1000 (sl_DL.txt), matching the manual LACC direct-with-shift base.

Status bits: Same as LACC (shared encoding): affected by SXM.

Words / Cycles: Words 1; Cycles 1 (single, operand in DARAM).

Cycle class: see Instruction Timing.

Example: LACI dma,shift loads Data(dma) left-shifted into ACC, as LACC does.

Description: Older mnemonic that loads the accumulator with a zero-extended 8-bit constant; the toolchain table gives it the short-immediate encoding of LACL.

Syntax: LACK #k

Operation: Same as LACL short immediate (shared opcode): 0 -> ACC(31-8); k -> ACC(7-0)

Operands: 0 <= k <= 255

Opcode: 1011 1001 kkkkkkkk (8-bit constant). Base hex 0xB900 (sl_DL.txt), matching the manual LACL short-immediate row.

Status bits: Same as LACL (shared opcode): not affected by SXM; operand is not sign-extended.

Words / Cycles: Words 1; Cycles 1 (single). Not repeatable.

Cycle class: see Instruction Timing.

Example: LACK #10h loads 010h into the accumulator.

Description: Loads the low accumulator with a data-memory word or an 8-bit constant and zero-fills the high half; never sign-extends.

Syntax: LACL dma (direct); LACL {ind} [,ARn] (indirect); LACL #k (short immediate)

Operation: (PC) + 1 -> PC. Direct/indirect: 0 -> ACC(31-16), (dma) -> ACC(15-0). Short immediate: 0 -> ACC(31-8), k -> ACC(7-0).

Operands: 0 <= dma <= 127; 0 <= n <= 7; 0 <= k <= 255; ind in {* *+ *- *0+ *0- *BR0+ *BR0-}

Opcode: Direct 0110 1001 0 ddddddd (0x6900); Indirect 0110 1001 1 ...; Short immediate 1011 1001 kkkkkkkk (0xB900). sl_DL.txt lists LACL as 0x0000, a format seed that matches neither form; the direct base is 0x6900 and the short-immediate base 0xB900 is carried under LACK.

Status bits: Not affected by SXM. The operand is treated as an unsigned 16-bit value.

Words / Cycles: Words 1; Cycles 1 (single, direct/indirect, operand in DARAM); short immediate is not repeatable.

Cycle class: IIA (LACL); I (LACL #k) - see Instruction Timing.

Cycle timing (SPRU056D ch. 6):

For the short immediate addressing modes, the LACL instruction is not repeatable.

Cycles for a Single Instruction (direct or indirect addressing)

• If the operand and the code are in the same SARAM block

Cycles for a Repeat (RPT) Execution (direct or indirect addressing)

• If the operand and the code are in the same SARAM block

Cycles for a Single Instruction (short immediate addressing)

Example: LACL DAT1 (DP = 6) loads Data(301h) into ACCL with ACCH zeroed.

Description: Loads the accumulator from data memory with a dynamic left shift taken from the four LSBs of TREG1.

Syntax: LACT dma (direct); LACT {ind} [,ARn] (indirect)

Operation: (PC) + 1 -> PC; (dma) x 2^TREG1(3-0) -> ACC; sign-extended only if SXM set

Operands: 0 <= dma <= 127; 0 <= n <= 7; ind in {* *+ *- *0+ *0- *BR0+ *BR0-}

Opcode: Direct 0110 1011 0 ddddddd; Indirect 0110 1011 1 .... Base hex 0x6B00 (sl_DL.txt), matches the manual direct row.

Status bits: Affected by SXM.

Words / Cycles: Words 1; Cycles 1 (single, operand in DARAM). Useful for denormalizing a floating-point number whose exponent fits in four bits.

Cycle class: IIA - see Instruction Timing.

Cycle timing (SPRU056D ch. 6):

Cycles for a Single Instruction

• If the operand and the code are in the same SARAM block

Cycles for a Repeat (RPT) Execution

• If the operand and the code are in the same SARAM block

Example: LACT DAT1 (DP = 6, SXM = 0, TREG1 = 14h) loads Data(301h) shifted by 4 into ACC.

Description: Older mnemonic for the long-immediate, shifted form of LACC.

Syntax: LALK #lk [,shift]

Operation: Same as LACC long immediate (shared opcode): lk x 2^shift -> ACC

Operands: -32768 <= lk <= 32767; 0 <= shift <= 16

Opcode: 1011 1111 1000 ssss then a 16-bit constant word. Base hex 0xBF80 (sl_DL.txt), matching the manual LACC long-immediate-with-shift row.

Status bits: Same as LACC (shared opcode): affected by SXM.

Words / Cycles: Words 2; Cycles 2 (single). Not repeatable.

Cycle class: see Instruction Timing.

Example: LALK #0F000h,1 loads the shifted constant into ACC, as LACC #lk,shift does.

Description: Loads the low accumulator from a memory-mapped register on page 0 without touching the DP; high half is zeroed.

Syntax: LAMM dma (direct); LAMM {ind} [,ARn] (indirect)

Operation: (PC) + 1 -> PC; (dma) -> ACC(15-0); 0 -> ACC(31-16). The nine MSBs of the address are forced to 0.

Operands: 0 <= dma <= 127; 0 <= n <= 7; ind in {* *+ *- *0+ *0- *BR0+ *BR0-}

Opcode: Direct 0000 1000 0 ddddddd; Indirect 0000 1000 1 .... Base hex 0x0800 (sl_DL.txt), matches the manual direct row.

Status bits: Not affected by SXM.

Words / Cycles: Words 1; Cycles 1 (single, MMR operand).

Cycle class: IIB - see Instruction Timing.

Cycle timing (SPRU056D ch. 6):

Cycles for a Single Instruction

• Add one more cycle for peripheral memory-mapped access

Cycles for a Repeat (RPT) Execution

** Add n more cycles for peripheral memory-mapped access

Example: LAMM BMAR loads the BMAR contents into ACC without modifying the DP.

Description: Loads an auxiliary register from data memory or from an 8-bit or 16-bit constant.

Syntax: LAR ARx, dma (direct); LAR ARx, {ind} [,ARn] (indirect); LAR ARx, #k (short immediate); LAR ARx, #lk (long immediate)

Operation: (PC) + 1 -> PC (2 for long immediate); (dma), k, or lk -> AR. The constant is treated as unsigned regardless of SXM.

Operands: 0 <= x <= 7; 0 <= dma <= 127; 0 <= n <= 7; 0 <= k <= 255; 0 <= lk <= 65535; ind in {* *+ *- *0+ *0- *BR0+ *BR0-}

Opcode: Direct 0000 0 AAA 0 ddddddd (AAA = ARX; base 0x0000); Indirect 0000 0 AAA 1 ...; Short immediate 1011 0 AAA kkkkkkkk (base 0xB000); Long immediate 1011 1111 0000 1 AAA then 16-bit constant (base 0xBF08). Base hex 0x0000 (sl_DL.txt) matches the direct base.

Status bits: Affected by NDX; not affected by SXM.

Words / Cycles: Words 1 (direct/indirect/short immediate) or 2 (long immediate); Cycles 2 (single, direct/indirect, source in DARAM); immediate forms are not repeatable.

Cycle class: XXVII (LAR); XXVIII (LAR ARn, #k); III (LAR ARn, #lk) - see Instruction Timing.

Cycle timing (SPRU056D ch. 6):

For the short and long immediate addressing modes, the LAR instruction is not repeatable.

Cycles for a Single Instruction (direct or indirect addressing)

• If the source operand and the code are in the same SARAM block

Cycles for a Repeat (RPT) Execution (direct or indirect addressing)

• If the source operand and the code are in the same SARAM block

Cycles for a Single Instruction (short immediate addressing)

• If the source operand and the code are in the same SARAM block

Cycles for a Single Instruction (long immediate addressing)

Example: LAR AR0,DAT16 (DP = 6) loads Data(310h) into AR0. In indirect mode a modification of the AR named by the instruction is ignored when it equals the ARP target.

Description: Older mnemonic for the short-immediate form of LAR (load auxiliary register with an 8-bit constant).

Syntax: LARK ARx, #k

Operation: Same as LAR short immediate (shared opcode): k -> AR

Operands: 0 <= x <= 7; 0 <= k <= 255

Opcode: 1011 0 AAA kkkkkkkk (AAA = ARX). Base hex 0xB000 (sl_DL.txt), matching the manual LAR short-immediate row.

Status bits: Same as LAR (shared opcode): affected by NDX; not affected by SXM.

Words / Cycles: Words 1; Cycles 2 (single). Not repeatable.

Cycle class: see Instruction Timing.

Example: LARK AR4,#01h loads 01h into AR4.

Description: Load-auxiliary-register-pointer mnemonic. Not documented within the provided source range; listed from the toolchain opcode table for completeness.

Syntax: not specified (outside source range)

Operation: not specified (outside source range)

Operands: not specified (outside source range)

Opcode: ASCII field row not specified (outside source range); base hex 0x8B88 (sl_DL.txt). Not cross-checkable against the source range.

Status bits: not specified (outside source range)

Words / Cycles: not specified (outside source range)

Cycle class: see Instruction Timing.

Example: not specified (outside source range)

Description: Loads the nine data-memory page-pointer bits from a data-memory word or a 9-bit constant.

Syntax: LDP dma (direct); LDP {ind} [,ARn] (indirect); LDP #k (short immediate)

Operation: (PC) + 1 -> PC. Direct/indirect: nine LSBs of (dma) -> DP. Short immediate: k -> DP.

Operands: 0 <= dma <= 127; 0 <= n <= 7; 0 <= k <= 511; ind in {* *+ *- *0+ *0- *BR0+ *BR0-}

Opcode: Direct 0000 1101 0 ddddddd (0x0D00); Indirect 0000 1101 1 ...; Short immediate 1011 110 kkkkkkkkk (9-bit constant, 0xBC00). sl_DL.txt lists LDP as 0x0001, a format seed; the direct base 0x0D00 is carried under LDPI and the short-immediate base 0xBC00 under LDPK.

Status bits: Affects DP.

Words / Cycles: Words 1; Cycles 2 (single, direct/indirect, source in DARAM); short immediate is not repeatable.

Cycle class: XXVII (LDP); XXVIII (LDP #k) - see Instruction Timing.

Cycle timing (SPRU056D ch. 6):

For the short immediate addressing modes, the LDP instruction is not repeatable.

Cycles for a Single Instruction (direct or indirect addressing)

• If the source operand and the code are in the same SARAM block

Cycles for a Repeat (RPT) Execution (direct or indirect addressing)

• If the source operand and the code are in the same SARAM block

Cycles for a Single Instruction (short immediate addressing)

• If the source operand and the code are in the same SARAM block

Example: LDP #0h clears the DP to page 0.

Description: Toolchain-internal name for the concrete direct encoding of LDP.

Syntax: LDPI dma (direct); LDPI {ind} [,ARn] (indirect)

Operation: Same as LDP direct/indirect (shared encoding): nine LSBs of (dma) -> DP

Operands: 0 <= dma <= 127; 0 <= n <= 7; ind in {* *+ *- *0+ *0- *BR0+ *BR0-}

Opcode: Direct 0000 1101 0 ddddddd; Indirect 0000 1101 1 .... Base hex 0x0D00 (sl_DL.txt), matching the manual LDP direct base.

Status bits: Same as LDP (shared encoding): affects DP.

Words / Cycles: Words 1; Cycles 2 (single, source in DARAM).

Cycle class: see Instruction Timing.

Example: LDPI dma loads the page pointer from the nine LSBs of Data(dma), as LDP does.

Description: Older mnemonic for the short-immediate form of LDP (load the page pointer from a 9-bit constant).

Syntax: LDPK #k

Operation: Same as LDP short immediate (shared opcode): k -> DP

Operands: 0 <= k <= 511

Opcode: 1011 110 kkkkkkkkk (9-bit constant). Base hex 0xBC00 (sl_DL.txt), matching the manual LDP short-immediate row.

Status bits: Same as LDP (shared opcode): affects DP.

Words / Cycles: Words 1; Cycles 2 (single). Not repeatable.

Cycle class: see Instruction Timing.

Example: LDPK #0h sets the DP to page 0.

Description: Loads a memory-mapped register on page 0 from any data-memory address given as a 16-bit source, leaving the DP unchanged.

Syntax: LMMR dma, #addr (direct); LMMR {ind}, #addr [,ARn] (indirect)

Operation: PFC -> MCS; (PC) + 2 -> PC; lk -> PFC; (src at PFC) -> (dst at lower 7 bits of dma) per repeat; PFC + 1 -> PFC; MCS -> PFC

Operands: 0 <= dma <= 127; 0 <= n <= 7; 0 <= addr <= 65535; ind in {* *+ *- *0+ *0- *BR0+ *BR0-}

Opcode: Direct 1000 1001 0 ddddddd then a 16-bit address word; Indirect 1000 1001 1 ... then the 16-bit address. Base hex 0x8900 (sl_DL.txt), matches the manual direct row.

Status bits: none affected.

Words / Cycles: Words 2; Cycles 2 (single, source in DARAM, destination MMR). With RPT the source address auto-increments.

Cycle class: XXIII - see Instruction Timing.

Cycle timing (SPRU056D ch. 6):

Cycles for a Single Instruction

• If the source operand and the code are in the same SARAM block ** Add one more cycle for peripheral memory-mapped register access

Cycles for a Repeat (RPT) Execution

• If the source operand and the code are in the same SARAM block *** Add n more cycles for peripheral memory-mapped register access

Example: LMMR DBMR,#300h loads DBMR from Data(300h).

Description: Loads the high half of the product register from data memory, leaving the low half unchanged.

Syntax: LPH dma (direct); LPH {ind} [,ARn] (indirect)

Operation: (PC) + 1 -> PC; (dma) -> PREG(31-16)

Operands: 0 <= dma <= 127; 0 <= n <= 7; ind in {* *+ *- *0+ *0- *BR0+ *BR0-}

Opcode: Direct 0111 0101 0 ddddddd; Indirect 0111 0101 1 .... Base hex 0x7500 (sl_DL.txt), matches the manual direct row.

Status bits: none affected.

Words / Cycles: Words 1; Cycles 1 (single, operand in DARAM). Useful for restoring PREG high after interrupts or calls when automatic context save is not used.

Cycle class: IIA - see Instruction Timing.

Cycle timing (SPRU056D ch. 6):

Cycles for a Single Instruction

• If the operand and the code are in the same SARAM block

Cycles for a Repeat (RPT) Execution

• If the operand and the code are in the same SARAM block

Example: LPH DAT0 (DP = 4) sets PREG high to F79Ch, keeping PREG low.

Description: Older mnemonic for the long-immediate form of LAR (load an auxiliary register with a 16-bit constant).

Syntax: LRLK ARx, #lk

Operation: Same as LAR long immediate (shared opcode): lk -> AR

Operands: 0 <= x <= 7; 0 <= lk <= 65535

Opcode: 1011 1111 0000 1 AAA then a 16-bit constant word (AAA = ARX). Base hex 0xBF08 (sl_DL.txt), matching the manual LAR long-immediate row.

Status bits: Same as LAR (shared opcode): affected by NDX; not affected by SXM.

Words / Cycles: Words 2; Cycles 2 (single). Not repeatable.

Cycle class: see Instruction Timing.

Example: LRLK AR4,#3FFFh loads 3FFFh into AR4.

Description: Restores a status register (ST0 or ST1) from data memory; the selector m chooses which register.

Syntax: LST #m, dma (direct); LST #m, {ind} [,ARn] (indirect)

Operation: (PC) + 1 -> PC; (dma) -> STm; dma(13-15) -> ARP regardless of n

Operands: 0 <= dma <= 127; m = 0 or 1; 0 <= n <= 7; ind in {* *+ *- *0+ *0- *BR0+ *BR0-}

Opcode: LST #0 direct 0000 1110 0 ddddddd (0x0E00); LST #0 indirect 0000 1110 1 ...; LST #1 direct 0000 1111 0 ddddddd (0x0F00); LST #1 indirect 0000 1111 1 .... sl_DL.txt lists LST as 0x0000, a format seed; the real form bases 0x0E00 and 0x0F00 are carried under LST0 and LST1.

Status bits: LST #0 affects ARB, ARP, C, CNF, DP, HM, OV, OVM, PM, SXM, TC, and XF but not INTM. For LST #1 the value loaded into ARB is also loaded into ARP.

Words / Cycles: Words 1; Cycles 2 (single, source in DARAM).

Cycle class: XXVII - see Instruction Timing.

Cycle timing (SPRU056D ch. 6):

Cycles for a Single Instruction

• If the source operand and the code are in the same SARAM block

Cycles for a Repeat (RPT) Execution

• If the source operand and the code are in the same SARAM block

Example: LST #0,60h (DP = 0) loads ST0 from Data(60h), leaving INTM and ARB unchanged.

Description: Toolchain mnemonic for the LST #0 form (restore ST0 from data memory).

Syntax: LST0 dma (direct); LST0 {ind} [,ARn] (indirect)

Operation: Same as LST #0 (shared opcode): (dma) -> ST0; dma(13-15) -> ARP

Operands: 0 <= dma <= 127; 0 <= n <= 7; ind in {* *+ *- *0+ *0- *BR0+ *BR0-}

Opcode: Direct 0000 1110 0 ddddddd; Indirect 0000 1110 1 .... Base hex 0x0E00 (sl_DL.txt), matching the manual LST #0 direct row.

Status bits: Same as LST #0 (shared opcode): affects ARB, ARP, C, CNF, DP, HM, OV, OVM, PM, SXM, TC, and XF but not INTM.

Words / Cycles: Words 1; Cycles 2 (single, source in DARAM).

Cycle class: see Instruction Timing.

Example: LST0 60h loads ST0 from Data(60h), as LST #0 does.

Description: Toolchain mnemonic for the LST #1 form (restore ST1 from data memory).

Syntax: LST1 dma (direct); LST1 {ind} [,ARn] (indirect)

Operation: Same as LST #1 (shared opcode): (dma) -> ST1; value loaded into ARB is also loaded into ARP

Operands: 0 <= dma <= 127; 0 <= n <= 7; ind in {* *+ *- *0+ *0- *BR0+ *BR0-}

Opcode: Direct 0000 1111 0 ddddddd; Indirect 0000 1111 1 .... Base hex 0x0F00 (sl_DL.txt), matching the manual LST #1 direct row.

Status bits: Same as LST #1 (shared opcode): the value loaded into ARB is also loaded into ARP.

Words / Cycles: Words 1; Cycles 2 (single, source in DARAM).

Cycle class: see Instruction Timing.

Example: LST1 00h (DP = 6) loads ST1 from Data(300h), as LST #1 does.

Description: Loads TREG0 from data memory in preparation for a multiply.

Syntax: LT dma (direct); LT {ind} [,ARn] (indirect)

Operation: (PC) + 1 -> PC; (dma) -> TREG0; if TRM = 0 also (dma) -> TREG1 and TREG2

Operands: 0 <= dma <= 127; 0 <= n <= 7; ind in {* *+ *- *0+ *0- *BR0+ *BR0-}

Opcode: Direct 0111 0011 0 ddddddd; Indirect 0111 0011 1 .... Base hex 0x7300 (sl_DL.txt), matches the manual direct row.

Status bits: Affected by TRM.

Words / Cycles: Words 1; Cycles 1 (single, operand in DARAM).

Cycle class: IIA - see Instruction Timing.

Cycle timing (SPRU056D ch. 6):

Cycles for a Single Instruction

• If the operand and the code are in the same SARAM block

Cycles for a Repeat (RPT) Execution

• If the operand and the code are in the same SARAM block

Example: LT DAT24 (DP = 8, TRM = 1) loads Data(418h) into TREG0.

Description: Loads TREG0 from data memory and adds the shifted product register to the accumulator.

Syntax: LTA dma (direct); LTA {ind} [,ARn] (indirect)

Operation: (PC) + 1 -> PC; (dma) -> TREG0; (ACC) + (shifted PREG) -> ACC; if TRM = 0 also -> TREG1 and TREG2

Operands: 0 <= dma <= 127; 0 <= n <= 7; ind in {* *+ *- *0+ *0- *BR0+ *BR0-}

Opcode: Direct 0111 0000 0 ddddddd; Indirect 0111 0000 1 .... Base hex 0x7000 (sl_DL.txt), matches the manual direct row.

Status bits: Affected by OVM, PM, and TRM; affects C and OV.

Words / Cycles: Words 1; Cycles 1 (single, operand in DARAM).

Cycle class: IIA - see Instruction Timing.

Cycle timing (SPRU056D ch. 6):

Cycles for a Single Instruction

• If the operand and the code are in the same SARAM block

Cycles for a Repeat (RPT) Execution

• If the operand and the code are in the same SARAM block

Example: LTA DAT36 (DP = 6, PM = 0, TRM = 1) loads Data(324h) into TREG0 and adds the shifted PREG to ACC.

Description: Like LTA but also moves the data word up one address (the DMOV delay), for on-chip RAM.

Syntax: LTD dma (direct); LTD {ind} [,ARn] (indirect)

Operation: (PC) + 1 -> PC; (dma) -> TREG0; (dma) -> dma + 1; (ACC) + (shifted PREG) -> ACC; if TRM = 0 also -> TREG1 and TREG2

Operands: 0 <= dma <= 127; 0 <= n <= 7; ind in {* *+ *- *0+ *0- *BR0+ *BR0-}

Opcode: Direct 0111 0010 0 ddddddd; Indirect 0111 0010 1 .... Base hex 0x7200 (sl_DL.txt), matches the manual direct row.

Status bits: Affected by OVM, PM, and TRM; affects C and OV.

Words / Cycles: Words 1; Cycles 1 (single, operand in DARAM). On external data memory the data move does not occur and the operation matches LTA.

Cycle class: V - see Instruction Timing.

Cycle timing (SPRU056D ch. 6):

Cycles for a Single Instruction

• If the operand and the code are in the same SARAM block

Cycles for a Repeat (RPT) Execution

• If the operand and the code are in the same SARAM block

Example: LTD DAT126 (DP = 7, PM = 0, TRM = 1) loads TREG0, copies Data(3FEh) to 3FFh, and accumulates the shifted PREG.

Description: Loads TREG0 from data memory and stores the shifted product register into the accumulator (no add).

Syntax: LTP dma (direct); LTP {ind} [,ARn] (indirect)

Operation: (PC) + 1 -> PC; (dma) -> TREG0; (shifted PREG) -> ACC; if TRM = 0 also -> TREG1 and TREG2

Operands: 0 <= dma <= 127; 0 <= n <= 7; ind in {* *+ *- *0+ *0- *BR0+ *BR0-}

Opcode: Direct 0111 0001 0 ddddddd; Indirect 0111 0001 1 .... Base hex 0x7100 (sl_DL.txt), matches the manual direct row.

Status bits: Affected by PM and TRM.

Words / Cycles: Words 1; Cycles 1 (single, operand in DARAM).

Cycle class: IIA - see Instruction Timing.

Cycle timing (SPRU056D ch. 6):

Cycles for a Single Instruction

• If the operand and the code are in the same SARAM block

Cycles for a Repeat (RPT) Execution

• If the operand and the code are in the same SARAM block

Example: LTP DAT36 (DP = 6, PM = 0, TRM = 1) loads TREG0 and stores the shifted PREG into ACC.

Description: Loads TREG0 from data memory and subtracts the shifted product register from the accumulator.

Syntax: LTS dma (direct); LTS {ind} [,ARn] (indirect)

Operation: (PC) + 1 -> PC; (dma) -> TREG0; (ACC) - (shifted PREG) -> ACC; if TRM = 0 also -> TREG1 and TREG2

Operands: 0 <= dma <= 127; 0 <= n <= 7; ind in {* *+ *- *0+ *0- *BR0+ *BR0-}

Opcode: Direct 0111 0100 0 ddddddd; Indirect 0111 0100 1 .... Base hex 0x7400 (sl_DL.txt), matches the manual direct row.

Status bits: Affected by OVM, PM, and TRM; affects C and OV. The C bit clears on a borrow, otherwise it sets.

Words / Cycles: Words 1; Cycles 1 (single, operand in DARAM).

Cycle class: IIA - see Instruction Timing.

Cycle timing (SPRU056D ch. 6):

Cycles for a Single Instruction

• If the operand and the code are in the same SARAM block

Cycles for a Repeat (RPT) Execution

• If the operand and the code are in the same SARAM block

Example: LTS DAT36 (DP = 6, PM = 0, TRM = 1) loads TREG0 and subtracts the shifted PREG from ACC.

Description: Multiply a data-memory value by a program-memory value and accumulate the shifted product into the ACC.

Syntax:

• Direct: MAC pma, dma
• Indirect: MAC pma, {ind} [,ARn]

Operation:

(ACC) + (shifted PREG) -> ACC
(dma) -> TREG0
(dma) x (pma, addressed by PFC) -> PREG
modify current AR and ARP as specified

Operands: 0 <= pma <= 65535; 0 <= dma <= 127; 0 <= n <= 7; ind: {* *+ *- *0+ *0- *BR0+ *BR0-}

Opcode: base hex 0xA200 (sl_M.txt).

Direct:    1 0 1 0 0 0 1 0 | 0 |      dma (7)        + 16-bit constant word
Indirect:  1 0 1 0 0 0 1 0 | 1 | indirect fields     + 16-bit constant word

Status bits: Affected by OVM, PM, and TRM. Affects C and OV.

Words / Cycles: 2 words; 3 cycles for a single instruction (both operands in DARAM/ROM).

Cycle class: XIX - see Instruction Timing.

Cycle timing (SPRU056D ch. 6):

Words: 2

Cycles for a Single Instruction

[1] If both operands are in the same SARAM block.

Cycles for a Repeat (RPT) Execution

[1] If both operands are in the same SARAM block.

Example: MAC 0FF00h,02h ; accumulate (shifted PREG), then Data(302h) x Prog(FF00h) -> PREG.

Description: Same as MAC, with a data move of the on-chip RAM operand after the multiply.

Syntax:

• Direct: MACD pma, dma
• Indirect: MACD pma, {ind} [,ARn]

Operation:

(ACC) + (shifted PREG) -> ACC
(dma) -> TREG0
(dma) x (pma, addressed by PFC) -> PREG
(dma) -> (dma)+1            ; data move, on-chip RAM only
modify current AR and ARP as specified

Operands: 0 <= pma <= 65535; 0 <= dma <= 127; 0 <= n <= 7; ind: {* *+ *- *0+ *0- *BR0+ *BR0-}

Opcode: base hex 0xA300 (sl_M.txt).

Direct:    1 0 1 0 0 0 1 1 | 0 |      dma (7)        + 16-bit constant word
Indirect:  1 0 1 0 0 0 1 1 | 1 | indirect fields     + 16-bit constant word

Status bits: Affected by OVM, PM, and TRM. Affects C and OV.

Words / Cycles: 2 words; 3 cycles for a single instruction (both operands in DARAM/ROM). The data move occurs only within on-chip data RAM blocks; with external data memory the instruction acts as MAC.

Cycle class: XXI - see Instruction Timing.

Cycle timing (SPRU056D ch. 6):

Words: 2

Cycles for a Single Instruction

[2] If both operands are in the same SARAM block [3] If both operands and the code are in the same SARAM block [4] Data move operation is not performed when operand2 is in external data memory.

Cycles for a Repeat (RPT) Execution

[1] If operand2 and code are in the same SARAM block [2] If both operands are in the same SARAM block [3] If both operands and the code are in the same SARAM block [4] Data move operation is not performed when operand2 is in external data memory.

Example: MACD 0FF00h,08h ; MAC plus Data(308h) copied to Data(309h).

Description: MAC from program memory with the pma taken from BMAR, plus a data move for on-chip RAM.

Syntax:

• Direct: MADD dma
• Indirect: MADD {ind} [,ARn]

Operation:

(BMAR) -> PFC
(ACC) + (shifted PREG) -> ACC
(dma) -> TREG0
(dma) x (pma, addressed by PFC) -> PREG
(dma) -> (dma)+1            ; data move, on-chip RAM only
modify current AR and ARP as specified

Operands: 0 <= dma <= 127; 0 <= n <= 7; ind: {* *+ *- *0+ *0- *BR0+ *BR0-}

Opcode: base hex 0xAB00 (sl_M.txt).

Direct:    1 0 1 0 1 0 1 1 | 0 |      dma (7)
Indirect:  1 0 1 0 1 0 1 1 | 1 | indirect fields

Status bits: Affected by OVM and PM. Affects C and OV.

Words / Cycles: 1 word; 2 cycles for a single instruction (both operands in DARAM/ROM). Acts as MADS when the data operand is a memory-mapped register or external memory.

Cycle class: XXII - see Instruction Timing.

Cycle timing (SPRU056D ch. 6):

Words: 1

Cycles for a Single Instruction

[2] If both operands are in the same SARAM block [3] If both operands and code are in the same SARAM block [4] Data move operation is not performed when operand2 is in external data memory.

Cycles for a Repeat (RPT) Execution

[1] If operand2 and code are in the same SARAM block [2] If both operands are in the same SARAM block [3] If both operands and code are in the same SARAM block [4] Data move operation is not performed when operand2 is in external data memory.

Example: MADD DAT7 ; pma from BMAR, accumulate, then Data move within on-chip RAM.

Description: MAC from program memory with the pma taken from BMAR, without the data move.

Syntax:

• Direct: MADS dma
• Indirect: MADS {ind} [,ARn]

Operation:

(BMAR) -> PFC
(ACC) + (shifted PREG) -> ACC
(dma) -> TREG0
(dma) x (pma, addressed by PFC) -> PREG
modify current AR and ARP as specified

Operands: 0 <= dma <= 127; 0 <= n <= 7; ind: {* *+ *- *0+ *0- *BR0+ *BR0-}

Opcode: base hex 0xAA00 (sl_M.txt).

Direct:    1 0 1 0 1 0 1 0 | 0 |      dma (7)
Indirect:  1 0 1 0 1 0 1 0 | 1 | indirect fields

Status bits: Affected by OVM and PM. Affects C and OV.

Words / Cycles: 1 word; 2 cycles for a single instruction (both operands in DARAM/ROM).

Cycle class: XX - see Instruction Timing.

Cycle timing (SPRU056D ch. 6):

Words: 1

Cycles for a Single Instruction

[1] If both operands are in the same SARAM block.

Cycles for a Repeat (RPT) Execution

[1] If both operands are in the same SARAM block.

Example: MADS DAT12 ; pma from BMAR, Data(30Ch) x Prog(FF00h) -> PREG.

Description: Modify the auxiliary registers and ARP; the referenced memory is unaffected.

Syntax:

• Direct: MAR dma
• Indirect: MAR {ind} [,ARn]

Operation:

Indirect addressing: modify current AR and ARP as specified
Direct addressing:   executes as a NOP

Operands: 0 <= n <= 7; ind: {* *+ *- *0+ *0- *BR0+ *BR0-}

Opcode: base hex 0x8B00 (sl_M.txt).

Direct:    1 0 0 0 1 0 1 1 | 0 |      dma (7)
Indirect:  1 0 0 0 1 0 1 1 | 1 | indirect fields

Status bits: Affected by NDX.

Words / Cycles: 1 word; 1 cycle for a single instruction. LARP (from the 'C2x set) is a subset of MAR: MAR *,4 equals LARP 4.

Cycle class: I - see Instruction Timing.

Cycle timing (SPRU056D ch. 6):

Words: 1

Cycles for a Single Instruction

Cycles for a Repeat (RPT) Execution

Example: MAR *,AR1 ; load ARP with 1.

Description: Multiply TREG0 by a data-memory value or a constant and store the product in PREG.

Syntax:

• Direct: MPY dma
• Indirect: MPY {ind} [,ARn]
• Short immediate: MPY #k
• Long immediate: MPY #lk

Operation:

Direct/indirect:   (TREG0) x (dma) -> PREG
Short immediate:   (TREG0) x k     -> PREG     ; k sign-extended, regardless of SXM
Long immediate:    (TREG0) x lk    -> PREG

Operands: 0 <= dma <= 127; 0 <= n <= 7; -4096 <= k <= 4095; -32768 <= lk <= 32767; ind: {* *+ *- *0+ *0- *BR0+ *BR0-}

Opcode: base hex 0x0000 (sl_M.txt; see notes - this does not match any MPY field row in the manual). Manual field rows:

Direct:          0 1 0 1 0 1 0 0 | 0 |      dma (7)            base 0x5400
Indirect:        0 1 0 1 0 1 0 0 | 1 | indirect fields         base 0x5400
Short immediate: 1 1 0 |            13-bit constant            base 0xC000
Long immediate:  1 0 1 1 1 1 1 0 1 0 0 0 0 0 0 0              base 0xBE80
                 + 16-bit constant word

Status bits: Affected by TRM. Not affected by SXM.

Words / Cycles: 1 word (direct, indirect, or short immediate), 2 words (long immediate); 1 cycle for a single direct/indirect instruction (DARAM), 2 cycles for long immediate. Not repeatable in the short or long immediate modes.

Cycle class: IIA (MPY); I (MPY #k); III (MPY #lk) - see Instruction Timing.

Cycle timing (SPRU056D ch. 6):

Words: 1 (Direct, indirect, or short immediate addressing); 2 (Long immediate addressing)

For the short and long immediate addressing modes, the MPY instruction is not repeatable.

Cycles for a Single Instruction (direct or indirect addressing)

[1] If the operand and the code are in the same SARAM block

Cycles for a Repeat (RPT) Execution (direct or indirect addressing)

[1] If the operand and the code are in the same SARAM block

Cycles for a Single Instruction (short immediate addressing)

Cycles for a Single Instruction (long immediate addressing)

Example: MPY DAT13 ; TREG0 x Data(40Dh) -> PREG.

Description: Accumulate the shifted PREG into the ACC, then multiply TREG0 by a data-memory value into PREG.

Syntax:

• Direct: MPYA dma
• Indirect: MPYA {ind} [,ARn]

Operation:

(ACC) + (shifted PREG) -> ACC
(TREG0) x (dma) -> PREG

Operands: 0 <= dma <= 127; 0 <= n <= 7; ind: {* *+ *- *0+ *0- *BR0+ *BR0-}

Opcode: base hex 0x5000 (sl_M.txt).

Direct:    0 1 0 1 0 0 0 0 | 0 |      dma (7)
Indirect:  0 1 0 1 0 0 0 0 | 1 | indirect fields

Status bits: Affected by OVM, PM, and TRM. Affects C and OV.

Words / Cycles: 1 word; 1 cycle for a single instruction (DARAM).

Cycle class: IIA - see Instruction Timing.

Cycle timing (SPRU056D ch. 6):

Words: 1

Cycles for a Single Instruction

[1] If the operand and the code are in the same SARAM block

Cycles for a Repeat (RPT) Execution

[1] If the operand and the code are in the same SARAM block

Example: MPYA DAT13 ; add shifted PREG to ACC, then TREG0 x Data(30Dh) -> PREG.

Description: Not specified (no dedicated entry in the provided source range). The toolchain opcode matches the MPY direct/indirect field row (base 0x5400).

Syntax: not specified in the provided source range.

Operation: not specified in the provided source range.

Operands: not specified in the provided source range.

Opcode: base hex 0x5400 (sl_M.txt). This equals the MPY direct/indirect opcode row in the manual: