CPU and Registers - wgrzegorz/c5xtools GitHub Wiki
CPU and Registers
Normative source: SPRU056D, chapter 3 and section 4.4.
The TMS320C5x central processing unit puts into hardware the operations that simpler processors leave to software or microcode: a single-cycle 16-bit by 16-bit multiply, barrel shifting, and address arithmetic. This page describes the four processing units that make up the CPU - the central arithmetic logic unit (CALU), the parallel logic unit (PLU), and the auxiliary register arithmetic unit (ARAU) - and then catalogs the CPU registers and the status and control registers, including the exact bit layout of ST0, ST1, PMST, and CBCR.
All registers and data paths are 16 bits wide unless stated otherwise.
1. Central arithmetic logic unit (CALU)
The CALU is the main data path. It is built from:
- a 16-bit by 16-bit parallel multiplier,
- a 32-bit two's-complement arithmetic logic unit (ALU),
- a 32-bit accumulator (ACC),
- a 32-bit accumulator buffer (ACCB),
- a product shifter (p-scaler) that shifts 0, 1, or 4 bits left or 6 bits right,
- a 0- to 16-bit left barrel shifter (prescaler, SFL),
- a 0- to 16-bit right barrel shifter (prescaler, SFR), and
- a 0- to 7-bit left barrel shifter (postscaler).
A typical ALU instruction fetches data from memory onto the data bus, passes it through the prescaler and the ALU, and moves the result into the ACC. One ALU input is always the ACC itself; the other comes from the PREG, the ACCB, or the prescaler output. The shifters let the CALU do numerical scaling, bit extraction, extended-precision arithmetic, and overflow prevention; they sit on the outputs of the PREG and the ACC.
1.1 Multiplier, PREG, and TREG0
The hardware multiplier produces a signed or unsigned 32-bit product in one machine cycle. Every multiply instruction except multiply-unsigned (MPYU) treats both operands as two's-complement numbers and yields a two's-complement result. One multiplier input is the memory-mapped temporary register TREG0; the other comes from the data bus or the program bus. The 32-bit result lands in the product register (PREG) and is then available to the ALU.
The LT instruction loads TREG0 with the first operand from the data bus, and MPY supplies the second operand. A product is available every two cycles except with a long immediate operand. The four multiply/accumulate instructions - MAC, MACD, MADD, and MADS - keep both operands flowing to the multiplier through the program and data buses; combined with RPT or RPTZ they become single-cycle multiply/accumulate steps, with coefficient addresses generated by the PC and data addresses by the ARAU. RPTZ additionally clears the ACC and the PREG. MACD and MADD include a data-move (DMOV) that copies the fetched value to the next higher data address, which supports filter delay lines (the DMOV does not work with external data memory). MPYU multiplies the unsigned contents of TREG0 by an unsigned data memory word for extended-precision work; SQRA and SQRS square a data value by feeding it to both multiplier inputs. Once computed, the PREG can be moved to the ALU or stored to memory with SPH (store product high) and SPL (store product low).
The product shift mode (PM field in ST1) controls the p-scaler on the PREG output:
| PM | P-scaler action on the PREG output |
|---|---|
| 00 | No shift. |
| 01 | Left-shifted 1 bit, LSB zero-filled. Compensates for the extra sign bit from multiplying two 16-bit two's-complement numbers. |
| 10 | Left-shifted 4 bits, 4 LSBs zero-filled. Used with MPY of a 13-bit (or shorter) immediate to drop the four extra sign bits. |
| 11 | Right-shifted 6 bits, sign extended, 6 LSBs lost. Allows up to 128 consecutive multiply/accumulates without overflow; the product is always sign extended regardless of SXM. |
The same PM shift is applied when the PREG is stored to data memory; the PREG contents themselves are left unchanged by the shift.
1.2 ALU and accumulators
The 32-bit ALU executes most arithmetic and logical functions in one clock cycle, writing its result into the ACC where further operations such as shifting can take place. The ACC splits into a high half (ACCH, bits 16-31) and a low half (ACCL, bits 0-15) for storage. The postscaler on the ACC output applies a 0- to 7-bit left shift while data is being driven to the data bus; the ACC itself is unchanged. On the high word the MSBs are lost and the vacated LSBs are filled from the low word; on the low word the LSBs are zero-filled.
The ACCB is a 32-bit temporary buffer. It gives a fast save of the ACC, can feed the ALU as an input, and supports the CRLT and CRGT instructions that leave the signed minimum or maximum of ACC and ACCB in both registers (setting the carry bit when the condition is met). The NORM instruction normalizes a fixed-point value in the ACC with left shifts; TREG1 can supply a variable prescaler shift for the ADDT, LACT, and SUBT instructions.
Overflow handling is governed by the overflow mode bit OVM in ST0. With OVM set, an overflow sets the overflow flag and saturates the ACC to the most positive value 7FFF FFFFh or the most negative value 8000 0000h, according to the direction of the overflow. With OVM cleared, the overflowed result is written to the ACC unmodified. Logical operations cannot overflow.
The ACC has a carry bit (C, in ST1) that makes extended-precision add and subtract efficient. It is affected by most arithmetic instructions and by the single-bit shift and rotate instructions, but not by loading the ACC, by logical operations, or by other non-arithmetic control instructions. A carry sets C; a borrow clears it. ADDC and ADCB add in the previous carry; SUBB and SBBB subtract using the logical inversion of the previous carry. ADD and SUB with a shift count of 16 are special: they can generate a carry or borrow but will not clear one that is not generated, which aids extended-precision arithmetic. C is set at reset and can be loaded by CLRC, LST #1, and SETC.
Sign extension of data entering the ACC through the scaling shifter is controlled by SXM in ST1. SXM also defines the shift-accumulator-right (SFR) instruction: with SXM = 1 SFR is an arithmetic right shift that preserves the sign; with SXM = 0 it is a logical shift that brings in a 0. SFL is unaffected by SXM and always shifts a 0 into the LSB. The SFLB, SFRB, RORB, and ROLB instructions operate on the 65-bit combination of ACC, ACCB, and carry.
1.3 Scaling shifters and TREG1
The prescaler has a 16-bit input from the data bus and a 32-bit output to the ALU, producing a left shift of 0 to 16 bits. The shift count is either a constant embedded in the instruction word or the value in TREG1 (a 5-bit register). The output LSBs are zero-filled; the MSBs are zero-filled or sign-extended according to SXM. Together with the p-scaler and postscaler, the prescaler supports numerical scaling, bit extraction, extended-precision arithmetic, and overflow prevention.
2. Parallel logic unit (PLU)
The PLU sets, clears, tests, or toggles bits in a control/status register or in any data memory location without disturbing the ACC or the PREG. It performs a read-modify-write: one operand is fetched from data memory, the second from a long immediate on the program bus or from the dynamic bit manipulation register (DBMR); the PLU then applies the logical operation defined by the instruction and writes the result back to the same data memory location.
The PLU can AND, OR, exclusive-OR, or load a 16-bit long immediate to a data location. The dynamic variants - APL (AND), OPL (OR), and XPL (exclusive-OR) - use the DBMR value instead of a long immediate. BIT tests an individual bit and CPL compares against a bit pattern; a match sets the test/control bit TC in ST1. APL, OPL, and XPL also set TC when the value written back is 0, allowing bits to be tested and cleared in one step. Because the PLU reaches all of data address space, it works on flags in RAM and on both on-chip and off-chip peripheral control registers.
3. Auxiliary register arithmetic unit (ARAU) and AR0-AR7
Eight 16-bit auxiliary registers (AR0-AR7) hold data memory addresses for indirect addressing or serve as general-purpose storage and counters. The current AR is selected by the 3-bit auxiliary register pointer (ARP) in ST0, loaded with a value of 0 to 7. The ARs and ARP can be loaded from data memory, from the ACC or PREG, or by an immediate operand; the ARs can be stored to data memory or used as CALU inputs. The ARs are memory-mapped and reside in data page 0.
The auxiliary register file is connected to the ARAU, which can autoindex the current AR while the data address is being formed - by plus or minus 1, or by the contents of the index register (INDX) - so the CALU is free to work in parallel. One ARAU input is INDX, the auxiliary register compare register (ARCR), or the eight LSBs of the instruction register (IREG); the other is the current AR. The ARAU implements 16-bit unsigned arithmetic, while the CALU implements 32-bit two's-complement arithmetic. BANZ and BANZD let an AR act as a loop counter.
ARAU functions. AR is the current auxiliary register; the arrow is TI's "is stored into" notation, so the destination is on the right.
| Operation | Description |
|---|---|
| $AR + INDX \rightarrow AR$ | Add the unsigned 16-bit INDX. Example: ADD *0+ |
| $AR - INDX \rightarrow AR$ | Subtract the unsigned 16-bit INDX. Example: ADD *0- |
| $AR + 1 \rightarrow AR$ | Increment by 1. Example: ADD *+ |
| $AR - 1 \rightarrow AR$ | Decrement by 1. Example: ADD *- |
| $AR \rightarrow AR$ | No modification. Example: ADD * |
| $AR + IR_{7:0} \rightarrow AR$ | Add an 8-bit immediate. Example: ADRK #55h |
| $AR - IR_{7:0} \rightarrow AR$ | Subtract an 8-bit immediate. Example: SBRK #55h |
| $AR + \mathrm{rc}(INDX) \rightarrow AR$ | Bit-reversed indexing: add INDX with reverse-carry propagation. Example: ADD *BR0+ |
| $AR - \mathrm{rc}(INDX) \rightarrow AR$ | Bit-reversed indexing: subtract INDX with reverse-carry propagation. Example: ADD *BR0- |
| $\mathrm{cmp}(AR, ARCR) \rightarrow TC$ | Per CMPR (=, <, >, !=) set the TC bit of ST1 if true, else clear it. Example: CMPR 3 |
| $AR = CBER ;\Rightarrow; CBSR \rightarrow AR$ | Reload the circular-buffer start address when the AR reaches the end; tested before the AR modification. |
INDX lets the address step by more than 1 (for example, down a matrix column) and maps the block dimension for bit-reversal addressing. ARCR bounds blocks of data and is compared with the current AR by CMPR. The 3-bit auxiliary register buffer (ARB) in ST1 holds the saved ARP across subroutine calls when the automatic context switch is not used. After a CALU load of an AR there is a two-instruction-cycle delay before that AR can be used for address generation.
Two circular buffers can run at once, controlled by the circular buffer control register (CBCR). To define one, load CBSR1 or CBSR2 with the buffer start address and CBER1 or CBER2 with the end address, load the AR with an address inside the range, then load CBCR with the AR number and set its enable bit (CENB1 or CENB2). On each AR update the AR value is compared with CBER before the update; if they are equal, CBSR is reloaded into the AR, otherwise the AR is modified as specified. For increment updates CBER must be greater than CBSR; for decrement updates CBER must be less than CBSR. The ARAU only tests for current AR = CBER and does not detect a step that jumps over CBER. Do not use the same AR for both circular buffers.
4. Status and control registers
The 'C5x has four status and control registers. CBCR and PMST are memory-mapped (they live in data memory page 0) and can be read, written, saved, and restored like any data memory location, including by the PLU. ST0 and ST1 are not in the memory map and cannot be reached by PLU instructions; they are written by LST and read by SST. PMST, ST0, and ST1 each have a one-level shadow register stack for automatic context save on an interrupt trap, restored by RETI or RETE. The INTM bit of ST0 and the XF bit of ST1 are not saved or restored on that automatic context save, so an interrupt service routine can toggle XF while the rest of the context is preserved.
After a status register update, the next two instructions must not depend on the reconfiguration the update caused.
4.1 Status register 0 (ST0)
| Bit(s) | Name | Reset | Function |
|---|---|---|---|
| 15-13 | ARP | X | Auxiliary register pointer. Selects the AR used in indirect addressing. When ARP is loaded, the previous ARP is copied to the ARB in ST1. Modified by indirect memory-reference instructions and by MAR or LST #0; LST #1 loads ARP from the ARB. |
| 12 | OV | 0 | Overflow flag. Indicates an ALU arithmetic overflow. Cleared by reset or a conditional branch on OV/NOV; once set it latches. Can be modified by LST #0. |
| 11 | OVM | X | Overflow mode. Enables (1) or disables (0) accumulator overflow saturation in the ALU. Set by SETC OVM, cleared by CLRC OVM, modifiable by LST #0. |
| 10 | - | 1 | Read as 1. |
| 9 | INTM | 1 | Interrupt mode. Globally masks (1) or enables (0) all maskable interrupts; no effect on RS and NMI. Unaffected by TRAP and LST #0, and not saved or restored on an automatic context save. Set by SETC INTM, INTR, RS, IACK, or a maskable trap; cleared by CLRC INTM or RETE. |
| 8-0 | DP | X | Data memory page pointer. Concatenated with the 7 LSBs of the instruction word to form a 16-bit direct address. Modified by LST #0 or LDP. |
4.2 Status register 1 (ST1)
| Bit(s) | Name | Reset | Function |
|---|---|---|---|
| 15-13 | ARB | XXX | Auxiliary register buffer. Holds the previous ARP value. Whenever ARP is loaded the old ARP is copied here (except with LST #0). LST #1 loads ARB and copies the same value to ARP, which helps restore context in a subroutine. |
| 12 | CNF | 0 | On-chip RAM configuration control. Maps on-chip dual-access RAM block 0 (DARAM B0) into data memory (CNF = 0) or program memory (CNF = 1). Set by SETC CNF, cleared by reset or CLRC CNF, modifiable by LST #1. |
| 11 | TC | X | Test/control flag. Stores the result of ALU or PLU bit-test operations; affected by APL, BIT, BITT, CMPR, CPL, NORM, OPL, and XPL. Governs conditional branch, call, and return. Set when a logical result is 0, a tested bit is 1, a compare is true, or a NORM exclusive-OR is true; cleared on the opposite conditions. Set by SETC TC, cleared by CLRC TC, modifiable by LST #1. |
| 10 | SXM | 1 | Sign-extension mode. Enables (1) or suppresses (0) sign extension of data entering the accumulator through the scaling shifter. ADDC, ADDS, SUBB, and SUBS suppress sign extension regardless of SXM. Set by reset or SETC SXM, cleared by CLRC SXM, modifiable by LST #1. |
| 9 | C | 1 | Carry bit. Indicates an ALU carry or borrow; affected by the single-bit shift and rotate instructions. C = 1 on an add carry (or a subtract that did not borrow); C = 0 on a subtract borrow (or an add that did not carry). ADD/SUB with a 16-bit shift can only set/clear it one way. Set by reset or SETC C, cleared by CLRC C, modifiable by LST #1. |
| 8-7 | - | 11 | Read as 1. |
| 6 | HM | 1 | Hold mode. Determines CPU behavior on an active HOLD. HM = 0: the CPU keeps executing from on-chip program memory but tri-states its external interface. HM = 1: the CPU halts internal execution. Set by reset or SETC HM, cleared by CLRC HM, modifiable by LST #1. |
| 5 | - | 1 | Read as 1. |
| 4 | XF | 1 | XF pin status. Sets the level of the external flag (XF) output pin (0 = low, 1 = high). Not saved or restored on an automatic context save. Set by reset or SETC XF, cleared by CLRC XF, modifiable by LST #1. |
| 3-2 | - | 11 | Read as 1. |
| 1-0 | PM | 00 | Product shift mode. Selects the p-scaler mode for the PREG output into the ALU (see the PM table in section 1.1). The PM shift also applies when the PREG is stored to data memory. Set by SPM or LST #1. |
4.3 Processor mode status register (PMST)
| Bit(s) | Name | Reset | Function |
|---|---|---|---|
| 15-11 | IPTR | 00000 | Interrupt vector pointer. Selects one of 32 2K-word pages where the interrupt vectors reside, allowing vectors to be remapped to RAM. Cleared at reset, so the reset vector is always at program address 0h. |
| 10-8 | - | 000 | Read as 0. |
| 7 | AVIS | 0 | Address visibility. AVIS = 0: the internal program address is driven to the pins (for tracing and interrupt-vector decode with IACK). AVIS = 1: the address lines do not follow the internal program address; control and data lines are unaffected and the bus keeps the last address. |
| 6 | - | 0 | Read as 0. |
| 5 | OVLY | 0 | RAM overlay. Enables (1) or disables (0) the on-chip single-access RAM (SARAM) in data memory space. Used with the RAM bit to configure the SARAM. |
| 4 | RAM | 0 | Program RAM enable. Enables (1) or disables (0) the on-chip SARAM in program memory space. Used with OVLY. |
| 3 | MP/MC | pin | Microprocessor/microcomputer. MP/MC = 0 maps on-chip ROM into program memory; MP/MC = 1 makes it not addressable. Set at reset to the logic level on the MP/MC pin, which is sampled at reset only. |
| 2 | NDX | 0 | Enable extra index register. NDX = 0 ('C2x mode): a 'C2x-compatible instruction that writes AR0 also writes INDX and ARCR. NDX = 1 ('C5x-enhanced): only AR0 is affected. |
| 1 | TRM | 0 | Enable multiple TREGs. TRM = 0 ('C2x mode): a 'C2x-compatible instruction that loads TREG0 also loads TREG1 and TREG2. TRM = 1 ('C5x-enhanced): only TREG0 is loaded. |
| 0 | BRAF | 0 | Block repeat active flag. BRAF = 1 while a block repeat is active; automatically set by RPTB and cleared when the block repeat counter (BRCR) decrements below 0. |
On-chip SARAM configuration from OVLY and RAM:
| OVLY | RAM | On-chip SARAM configuration |
|---|---|---|
| 0 | 0 | Disabled; SARAM is not addressable. |
| 0 | 1 | Mapped into program space. |
| 1 | 0 | Mapped into data space. |
| 1 | 1 | Mapped into both program and data spaces. |
4.4 Circular buffer control register (CBCR)
| Bit(s) | Name | Reset | Function |
|---|---|---|---|
| 15-8 | Reserved | - | Reserved. |
| 7 | CENB2 | 0 | Circular buffer 2 enable (0 = disabled, 1 = enabled). |
| 6-4 | CAR2 | - | Circular buffer 2 auxiliary register. Selects which of AR0-AR7 is assigned to circular buffer 2. |
| 3 | CENB1 | 0 | Circular buffer 1 enable (0 = disabled, 1 = enabled). |
| 2-0 | CAR1 | - | Circular buffer 1 auxiliary register. Selects which of AR0-AR7 is assigned to circular buffer 1. |
5. Summary of registers
CPU registers (other than ST0 and ST1), peripheral registers, and I/O ports occupy data memory space. The table below summarizes the CPU registers and the key memory-mapped registers.
| Register | Width | Purpose |
|---|---|---|
| ACC | 32 | Accumulator; destination for ALU results and one ALU input. |
| ACCB | 32 | Accumulator buffer; fast ACC save and an alternate ALU input. |
| ACCH / ACCL | 16 / 16 | High and low halves of the ACC for storage. |
| AR0-AR7 | 16 each | Auxiliary registers; indirect-address pointers, counters, or general storage. |
| ARCR | 16 | Auxiliary register compare register; address-boundary comparison with CMPR. |
| BMAR | 16 | Block move address register; indirect second-operand address for block moves and multiply/accumulate. |
| RPTC | 16 | Repeat counter register; count for the single-instruction repeat (RPT/RPTZ). Avoid writing to it directly. |
| BRCR | 16 | Block repeat counter register; count for the block repeat feature. |
| PASR | 16 | Block repeat program address start register; start of the repeated block (loaded by RPTB). |
| PAER | 16 | Block repeat program address end register; end of the repeated block (loaded by RPTB). |
| CBSR1 / CBSR2 | 16 each | Circular buffer start registers. |
| CBER1 / CBER2 | 16 each | Circular buffer end registers. |
| CBCR | 16 | Circular buffer control register; buffer enables and AR assignments (see section 4.4). |
| DBMR | 16 | Dynamic bit manipulation register; run-time mask for PLU operations. |
| GREG | 16 | Global memory allocation register; allocates part of local data space as global memory. |
| INDX | 16 | Index register; step value for ARAU address updates and bit-reversal block dimension. |
| IREG | 16 | Instruction register; holds the opcode being executed. |
| IMR | 16 | Interrupt mask register; masks individual interrupts. |
| IFR | 16 | Interrupt flag register; current interrupt status. |
| PMST | 16 | Processor mode status register; processor status and control (see section 4.3). |
| PREG | 32 | Product register; result of a multiply; high and low words individually accessible. |
| ST0 | 16 | Status register 0 (see section 4.1). |
| ST1 | 16 | Status register 1 (see section 4.2). |
| TREG0 | 16 | Temporary register; one multiplier multiplicand. |
| TREG1 | 5 | Temporary register; dynamic shift count for the prescaler. |
| TREG2 | 4 | Temporary register; dynamic bit address for the BITT instruction. |
I/O space (PA0-PA15) addresses 16 locations (50h-5Fh) that can be read into the CALU, written from the ACC, acted on by the PLU, or accessed with IN and OUT. Peripheral blocks (timer, serial ports, host port interface, wait-state generators) add their own memory-mapped registers; those are documented with each peripheral.
License
MIT - (c) 2026 Grzegorz Worona [email protected]. See LICENSE.