Processes - vineethkumarv/SystemVerilog_Course GitHub Wiki

Process is a built in class of system verilog that allows one process to control and access the other processes/threads.A process has the following by default.

 class process;
 typedef enum { FINISHED, RUNNING, WAITING, SUSPENDED, KILLED } state; 
 static function process self();
 function state status();
 function void kill();
 task await();
 function void suspend();
 function void resume();
 function void srandom( int seed );
 function string get_randstate();
 function void set_randstate( string state );
 endclass  

Here you can find some more details about fine grain processes.