Interface Interview Questions - vineethkumarv/SystemVerilog_Course GitHub Wiki

  1. How does the clocking block handles synchronous reset?

Synchronous reset is sampled only with respect to clock event. When reset is enabled, it will be effective only after next active clock edge.

 clockingblock  TB_CB @(posedge clk)   
 default input #1step output #0;   
 input rst;
 output a,b;
 input y;

Note: The clocking block is only designed to handle synchronous reset - it should happen only be based on clock event. Reset in clocking block should be handled elsewhere. If the clocking block outputs are variables, you can procedurally assign them outside of a clocking block on a reset.

  1. How does the modport handle asynchronous reset?

Asynchronous Reset

In asynchronous reset sampling is done by independent of clk. When reset is enabled ,it will be effective immediately within the same the clock edges.

image

                                         Fig 1: Design example

Here, in this example there are three signals a,b and c. 'a' is continuous signal and asynchronous. 'b' and 'c' are synchronous signals. Using modport we can change the asynchronous signal 'a' to synchronous signal.
modport TB_MP(TB_CB , output a);

Note: In Modport, the design can handled with asynchronous reset. The asynchronous reset will be happen at any time.