Loops

A Loop is nothing but statements that need to be run more than once are included in the loop instead of writing the statements repeatedly. Loops will run multiple times based on conditional statements, If the condition is always true then it becomes an infinite loop and the system will hang.

                      Loops variations

loops cheat sheet

S.No.	Loops_variants	Explanation
1.	while	Repeats the set of statements based on condition
2.	do_while	Once runs the statements without checking the condition then behaves as while
3.	repeat	Repeats the statements only a particular number of times
4.	for_loop	Similar to while but more compact than while
5.	foreach	Only Used to traverse through every element of array
6.	forever	Repeats the statements throughout simulation

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1. while

In a while loop, first we need to check the condition then only we can execute the statements. We need to initialize the variable in the condition before execution.
A while loop first checks the condition is true and then executes the statements if it is true. If the condition is false, the loop ends right there.

Syntax -
while(condition)begin
Statements;
end

Flowchart:

                                     Fig -1: Flowchart: while loop

Example -

Here, the example shows the print of a statement of 5 times using the while loop.

Code snap

int apple = 1; //int data type and variable name is apple

initial begin  //procedural blocks
 $display("-----while loop output ---");
while (apple <6) //while loop and condition
  begin
 $display("\t value of apple = %0d", apple);
 apple++;
end  
end

Output snap

The below figure shows the output of the while loop

                              fig-1:Output-while loop

GitHub lab Code link:- https://github.com/muneeb-mbytes/SystemVerilog_Course/blob/b7_Team_SiliconCrew/loops/while/while_basic/while_basic.sv

GitHub lab output link:- https://github.com/muneeb-mbytes/SystemVerilog_Course/blob/b7_Team_SiliconCrew/loops/while/while_basic/while_basic_log.log

Declare variable inside the loop

We can declare variables inside the loop. But that variable is a local variable, only we can use it inside the loop if can't use it out of the loop. If we use the variable out of the loop it will through an error.

Example -

The below example show the difference between the local and global variable. There are two variables are there one is local (a) and another one is global(x). a is the local variable for a first while loop. We can not use it outside that particular loop in which it is declared. x is a global variable, we can use it out of the loop.

Code Snap

int x = 2; // variable declare  
initial begin  
while ( x<5)begin  
int a;  // declare the variable inside the loop  
$display ("Iteration = %0d",x);  
$display ("a is a local variable");  
$display ("The size of a = %0d",$size(a));  
$display ("------------------------------");  
// a is a local variable. We can't use it out of the loop.  
x++;    // incrementing the x  
end  
// After the execution of the above loop. The value of x = 4 .  

while (x<8)begin  
 $display ("x is a global varaible ");  
 $display ( "The value of x = %0d",x);  
 $display ("------------------------");  
x++;  
end  
end  

Output Snap

The below figure shows the output of the declaring the variable inside the loop

                               fig-2:Output-while -declare variable inside loop

GitHub Lab Code link:- https://github.com/muneeb-mbytes/SystemVerilog_Course/blob/b7_Team_SiliconCrew/loops/while/while_local_var/whil.sv

GitHub Lab Output link:- https://github.com/muneeb-mbytes/SystemVerilog_Course/blob/b7_Team_SiliconCrew/loops/while/while_local_var/while_variable_log.log

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2. do-while

In the do-while loop, first execute the condition once and then check whether the condition is true or not. If the condition is true, the set of statements is executed until the condition turns out to be false. If the condition is false the loop ends right there.

Syntax -
do begin
Statements;
end
while(condition)begin
Statements;
end

Flowchart:

                                Fig - 2: Flowchart: do while loop

Example -

The below example shows code to understand the working of do - while loop.

Code Snap

 int apple = 1; //int data type and variable name is apple
 initial begin //procedural block
 $display("------do while output ---");
 do //do statements
begin
 $display("\t Value of apple = %0d", apple);

 apple = apple +1;
end      
while(apple<6); //while loop condition    
end     

Output Snap

The below figure shows the output of do while loop

                     fig-3: Output-do while loop

GitHub Lab Code link:- https://github.com/muneeb-mbytes/SystemVerilog_Course/blob/b7_Team_SiliconCrew/loops/do_while/do_while.sv

GitHub Lab Output link:- https://github.com/muneeb-mbytes/SystemVerilog_Course/blob/b7_Team_SiliconCrew/loops/do_while/do_while.sv

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3.repeat

This loop is used for repeating statements or operations for a fixed given number of times.

Syntax -
repeat(no. of times)begin
statements;
end

Example -

The below example shows the working of the repeat loop. Here, there are three statements inside the repeat loop. the repeating is for 4 times.

Code Snap

module repeat_code;  
initial begin ;  
 repeat(4)begin   // Repeat the statements inside 4 times  
   $display ("Good morning");  
   $display ("Keep shining");  
   $display ("--------------");  
 end  
end  

Flowchart:

                                Fig -3: Flowchart: repeat loop

Output Snippet

The below figure shows the output of the repeat loop

                  fig-4:Output-repeat loop

GitHub Code Lab link:- https://github.com/muneeb-mbytes/SystemVerilog_Course/blob/b7_Team_SiliconCrew/loops/repeat/repeat_normal/repeat.sv

GitHub Lab Output link:- https://github.com/muneeb-mbytes/SystemVerilog_Course/blob/b7_Team_SiliconCrew/loops/repeat/repeat_normal/repeat_code_log.log

Implementation of repeat loop using for loop
We can implement a repeat loop using other loops also. Below example will show the implementation of a repeat loop using for loop.

Example -

Same as the above example, here we are repeating these same statements using them for a loop.

Code Snippet

 initial begin  
  for (int i = 1;i<=4;i++)begin   // for loop initialization, repeat the statements inside it for  
     $display ("Good morning");   // 4 times (i =1,2,3,4)  
     $display ("Keep Shining");  
     $display ("------------");  
   end  
end  

Output Snap

The below figure shows the output of the repeat loop by using for loop

                   fig-5: Output - Implement repeat using for loop

GitHub Lab Code link:- https://github.com/muneeb-mbytes/SystemVerilog_Course/blob/b7_Team_SiliconCrew/loops/repeat/repeat_using_for_loop/repeat_for.sv

GitHub Lab Output link:- https://github.com/muneeb-mbytes/SystemVerilog_Course/blob/b7_Team_SiliconCrew/loops/repeat/repeat_using_for_loop/repeat_for_log.log

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4.for loop

For loop is simply a more compact form of while loop. In for loop assignment, there are three parts:

• Initialization - initialize the required variables for running the loop.
• condition - based on this condition the number of repetitions of for loop is dependent.
• modifier - incrementing/decrementing the variables.

Syntax:
for ( Initialization; condition; modifier )
begin
statement1;
statement2
.
.
statementN;
end

Example:

      for (int i=1;i<=5;i++)    
      begin     
      $display(" Iteration %0d ",i);     
      end   
      $display(" out of loop ");  

In the above example, i is the variable initialized and declared as 1, here i is the local scope only means we can't use i out of for loop. In condition i should be less than or equal to 5 means for loop statements will be executed if the value of i is matched with condition or else comes out of the loop and the last part is the modifier which is incrementing i value by 1.

Flowchart:

                         Flowchart.4- for loop flowchart  

output:

                         Fig.6 - for loop output

As per the flowchart initially, i is 1 so the condition satisfies and performs display statement and prints as "iteration 1" and then goes to modifier and increments i, check the condition again and so on till i=5, now after 5 i is incremented to 6 then checks condition which is failed so comes out of the loop.

Github lab code link: https://github.com/muneeb-mbytes/SystemVerilog_Course/blob/b7_Team_SiliconCrew/loops/for/for_loop/for_code.sv
Github lab output link: https://github.com/muneeb-mbytes/SystemVerilog_Course/blob/b7_Team_SiliconCrew/loops/for/for_loop/for_loop_output.log

Note: If you use a local scope variable outside then the compiler throughs an error as shown below.

     Fig.7 - error of for loop local scope variable usage out of loop

---

Nested for loop

Syntax:
for ( Initialization ; condition; modifier )
begin
statements; for ( Initialization ; condition ; modifier ) begin
statements; end
end

Example:

      for (int i=1;i<=2;i++)   
      begin   
      $display("\n\t%0d Table:\n",i);   
      for(int j=1,k=0;j<=10;j++)    
      begin   
      k=i*j;   
      $display("\t %0d X %0d = %0d",i,j,k);   
      end   
      end   

In the above example we are using nested for loop to print tables, so took i as table number and j for going from 1-10 and k to store the value of multiplication. Here observe that j & k are used at the same initialization and you can do the same for conditions and modifiers also to have multi variables at a time.

output:

     Fig.8 - nested for loop output  

In this i,j& k are used as i X j = k, so i is range from 1-2 and each has j from 1-10 and k is storing and printing using display statements.

GitHub lab code link: https://github.com/muneeb-mbytes/SystemVerilog_Course/blob/b7_Team_SiliconCrew/loops/for/nested_for/table_for_loop.sv
GitHub lab output link: https://github.com/muneeb-mbytes/SystemVerilog_Course/blob/b7_Team_SiliconCrew/loops/for/nested_for/tabe_for_loop_output.log

Advantages:

• Readable
• syntax will be easier(can mention all initialization,condition, modifier in a single place)

limitations:

• variables initialized are only local.

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5.foreach

This loop is an upgraded version of for loop for traversing through each element of an array. This iterates through index 0 till the size of an array mentioned.

foreach is a shorter version of the following for loop
for(int i=0;i<$size(array);i++)

Syntax:
foreach(array[i])
begin
statement1;
statement2
.
.
statementN;
end

Example:

      int array[5]   
      foreach(array[i])     
      begin      
      array[i]=i;    
      $display("\tarray[%0d]=%0d",i,array[i]);     
      end     
      $display(" out of loop ");   

In the above example, a fixed array of size 5 is taken, using a foreach loop to traverse through each element, and executes the statements of the foreach loop from array[0] to array[4].

Flowchart:

           Flowchart-5.foreach loop flowchart  

output:

          Fig.9 - foreach loop output  

As per the flowchart initially checks for the size of the array, as it is >0, so proceeds to execution of foreach statements i.e., assigns array[0]=0 and displaying the same and then increments i value by 1 and repeats the same until array[4]. Then at array[5] condition is failing because the array size is 5 only (i.e., 0,1,2,3,4) comes out of loop.

Github lab code link: https://github.com/muneeb-mbytes/SystemVerilog_Course/blob/b7_Team_SiliconCrew/loops/foreach/foreach_loop/foreach_loop.sv Github lab output link: https://github.com/muneeb-mbytes/SystemVerilog_Course/blob/b7_Team_SiliconCrew/loops/foreach/foreach_loop/foreach_loop_log.log

The same functionality of above program we can achieve by using for loop as following line replaced with foreach.

for(int i=0;i<$size(array);i++)

The following is the snap of output of foreach using for loop output of foreach using for loop:

     Fig.10 - foreach using for output

Github lab code link: https://github.com/muneeb-mbytes/SystemVerilog_Course/blob/b7_Team_SiliconCrew/loops/foreach/foreach_using_for/foreach_using_for.sv
Github lab output link: https://github.com/muneeb-mbytes/SystemVerilog_Course/blob/b7_Team_SiliconCrew/loops/foreach/foreach_using_for/foreach_using_for_log.log

Note: we can use nested foreach similarly as used in nested for loop and can access multidimensional arrays.

Advantages:

• syntax is easier.
• Readable

limitations:

• It is only used for arrays
• Modifier is not accessible(if we want to store array only in even positions then foreach not good option)
• Cannot traverse through array in reverse fashion

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6.forever

The forever loop name itself says that it will run forever i.e., throughout the simulation or forcefully shut down the forever loop.
It is similar to the always procedural block in System Verilog but generally, it's not possible to use always in classes to achieve that concept we can make use of this forever loop.
If we use a forever loop without force stop the compiler will hang. There are two ways to stop forever, they are

• $finish;

• break;

• forever with $finish:

forever loop doesn't have any conditions as the number of times to repeat the loop is infinite so no condition is needed. Syntax:
forever
begin
statement1;
statement2
.
.
statementN;
end

Example:

      forever   
      begin    
      $display("\t @ %0d ns Iteration %0d",$time,a);   
      a++;   
      #4;   
      end   
      initial begin   
      #20 $display("\n\t@ %0d ns Stopped using $finish",$time);   
      $finish;   
      end   

In the above example, forever is used which is having display statement and increment a and a 4ns delay for every repetition like that it will run forever but in another initial block there is $finish which will stop the simulation so this stops the forever also.

Flowchart:

           Flowchart-6.forever with finish flowchart  

output:

                 Fig.11 - forever with finish output  

As the forever doesn't have any condition it simply enters and displays a value and then a is incremented and a 4ns delay is introduced so for every 4ns the output is getting printed and at 20 ns $display and prints stopped using $finish is executed in second initial module as well as $finish is called in which will terminate the simulation.

Github lab code link: https://github.com/muneeb-mbytes/SystemVerilog_Course/blob/b7_Team_SiliconCrew/loops/forever/forever_loop_finish/forever_loop.sv
Github lab output link: https://github.com/muneeb-mbytes/SystemVerilog_Course/blob/b7_Team_SiliconCrew/loops/forever/forever_loop_finish/forever_loop_output.log

• forever with break:

Syntax:
forever
begin
statement1;
statement2
.
.
statementN;
end

Example:

      forever   
      begin   
      $display("\t @ %0d ns Iteration %0d",$time,a);   
      a++;   
      #4;   
      if(a>8)   
      break;   
      end   
      $display("\n\t@ %0d ns Stopped using break",$time);    
      end   

This is similar example of forever with $finish but here we have used break condition instead of $finish based on a value greater than 8.

Flowchart:

           Flowchart-4.forever using break flowchart  

output:

     Fig.12 - forever with break output  

As the forever doesn't have any condition it simply enters and displays a value and then a is incremented and a 4ns delay is introduced so for every 4ns the output is getting printed after a value greater than 8 then enters into if block which has a break which moves simulator to out of the loop.

Github lab code link: https://github.com/muneeb-mbytes/SystemVerilog_Course/blob/b7_Team_SiliconCrew/loops/forever/forever_loop_break/forever_loop.sv
Github lab output link: https://github.com/muneeb-mbytes/SystemVerilog_Course/blob/b7_Team_SiliconCrew/loops/forever/forever_loop_break/forever_loop_output.log

advantages:

• we cant use always block inside an always or a class there this forever is used and can achieve the same job

limitations:

• If we don't quit the forever then the simulator will hang.

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