06.Control Flow - vineethkumarv/SystemVerilog_Course GitHub Wiki
Fig -1: Control Flow
Control flow
Conditional Statements
Conditional statements are used to check whether the statements in the blocks are executed or not. Conditional statements create the block of statements. If the expression given is -
true - Execute the set of statements in the block.
false - the statements inside that block will not be executed.
else - if the expressions are false then the else block statements will execute at last.
There are different types of conditional statements. These are --
Cheat Sheet
| S.No | Conditional Statement |
|---|---|
| 1. | if |
| 2. | if-else |
| 3. | if-else ladder |
| 4. | unique if |
| 5. | unique0 if |
| 6. | priority if |
1. if without else
fig -2: if flow chart
This conditional statement is used for the basic codes where only need to make a decision by giving one condition. If the expression in the condition is -
true - execute the statements in the block.
false - will not execute the statement.
Syntax
if(condition)begin
Statements;
end
Note
For more than one statement in conditional blocks, need to use begin end block. Statements inside the begin end block execute in a sequential manner.
Example -
Here, the variable declare is a and value assigned to it is 10. The compiler will check the if conditional expression and condition are true a=10. So, the compiler will execute the set of statements inside the if block.
Code snippet
bit [3:0]a;
initial begin
a=10;
$display ("Value of a = %0d",a);
if (a==10)begin
$display ("if the expression is true, Successfully entered into the if block");
$display ( "a is equal to 10 " );
end
$display("out of if block");
end
Output Snap
The below figure shows the output of if conditional statement.
fig -1 : Output - if
GitHub Lab Code link:- https://github.com/muneeb-mbytes/SystemVerilog_Course/blob/b7_Team_SiliconCrew/conditional_statement/if_variants/if/if_code.sv
GitHub Lab Output link:- https://github.com/muneeb-mbytes/SystemVerilog_Course/blob/b7_Team_SiliconCrew/conditional_statement/if_variants/if/if_code_log.log
2. if else
fig -3: Flow chart-if else
This conditional statement has two sets of statements, one in the if block and another in the else block. If the expression in the if block is true, statements inside it will execute, or if the expression is false, statements inside the else block will execute.
else block doesn't check any expression to execute statements inside it, it just executes after if the expression is false.
Syntax
if(condition) begin
Statement1;
Statement2;
------
StatementN;
end
else begin
Statement1;
Statement2;
---------
StatementN;
end
Example -
Here the variable declares a is byte type(signed) and the value assigned to it is -1. If the conditional expression is false as a is less than 0.
Code Snippet
byte a;
initial begin
a = -1;
$display ("Assign the value of a = %0d ",a);
$display("-------------------------------------");
if(a>0)begin //false
$display ("Successfully enters into if block");
$display ("a is a positive number");
$display ("----------------------------------");
end
else
$display ("Number is negative");
$display ("Out of if else block");
end
Output Snap
The below figure shows the output of if-else conditional statement.
fig -2 : Output -if else
GitHub Lab Code link:- https://github.com/muneeb-mbytes/SystemVerilog_Course/blob/b7_Team_SiliconCrew/conditional_statement/if_variants/if_else/if_else.sv
GitHub Lab Output link:-https://github.com/muneeb-mbytes/SystemVerilog_Course/blob/b7_Team_SiliconCrew/conditional_statement/if_variants/if_else/if_else_log.log
3. if else ladder
fig-4 :flow chart-if else ladder
This conditional statement helps us to decide among multiple options or expressions. As soon as the expression becomes true, the statements inside it execute and the remaining code blocks are bypassed. If none of the expressions is true, the else block executes.
else block is an optional block in the ladder. It is used to avoid confusion in code.
Syntax
if(condition) begin
Statement1;
Statement2;
------
StatementN;
end
elseif begin
Statement1;
Statement2;
------
StatementN;
end
else begin
Statement1;
Statement2;
---------
StatementN;
end
a. without else
Sequentially all the conditional expressions will be checked. The compiler will execute the set of statements that has valid condition expression.
Example -
The below example has three variables a,b and c. The value assigned to them is 10,12 and 13. the compiler will check the conditional expression one after the other. Here the second conditional expression is true or valid. The output will be the set of statements inside the else if block.
Code Snippet
int a,b,c;
initial begin
a = 10;
b = 12;
c = 13;
$display ("Assign the value of a = %0d , b= %0d , c =%0d " ,a,b,c);
$display ("------------------------------------------------------");
if (a>b)begin //false
$display ("Successfully enters into if block ");
$display ("Value of a < b");
$display ("----------------------------------");
end
else if (b<c)begin //true
$display ("Successfully enters into else if block ");
$display ("value of b<c");
$display ("----------------------------------------------------");
end
else if (c<0) begin //false
$display ("Successfully enters into second elseif block ");
$display ("c is a negative number ");
$display ("--------------------------------------------");
end
$display ("Out from ladder block");
end
output Snap
The below figure shows the output of the if else ladder without the else conditional statement.
fig -3: output - if else ladder without else
GitHub Lab Code link:-https://github.com/muneeb-mbytes/SystemVerilog_Course/tree/b7_Team_SiliconCrew/conditional_statement/if_variants/if_else_ladder/if_else_ladder_withoutelse
GitHub Lab Output link:- https://github.com/muneeb-mbytes/SystemVerilog_Course/blob/b7_Team_SiliconCrew/conditional_statement/if_variants/if_else_ladder/if_else_ladder_withoutelse/if_elseif_log.log
b. with else
When none of the conditional expressions is true, the compiler will execute the set of statements of the else block.
Example
Here the example shows the execution of the else block.
Code snippet
int a, b,c;
initial begin
a = -12;
b = 12;
c = 10;
$display ("Assign the value of a =%0d b = %0d c = %0d ", a,b,c);
$display ("------------------------------------------------------");
if (a>0) //false condition
begin`
$display ("Entered into if block ");
$display ("a is a negative number");
end
else if (a==0) begin // false condition
$display ("Entered into first elseif block ");
$display ("a is a negative number ");
end
else if (b<c)begin // false condition
$display ("Entered into second else if block ");
$display ("b is less than c ");
end
else begin
$display ("None of the condition is true in if-else if blocks ");
$display ("-------------------------------------------------");
end
$display ("Out of the conditional block ");
end
output Snap
The below figure shows the output of the if-else ladder with else conditional statement.
fig -4: Output-if else ladder with else
GitHub Lab Code link:- https://github.com/muneeb-mbytes/SystemVerilog_Course/blob/b7_Team_SiliconCrew/conditional_statement/if_variants/if_else_ladder/if_else_ladder_withelse/if_elseif_else.sv
GitHub Lab Output link:- https://github.com/muneeb-mbytes/SystemVerilog_Course/blob/b7_Team_SiliconCrew/conditional_statement/if_variants/if_else_ladder/if_else_ladder_withelse/if_elseif_else_log.log
In SystemVerilog, there are three versions of a conditional statement updated. These are -
4. unique if
fig-5 :flow chart:unique_if
This is the updated conditional statement. In a unique, if conditional statement, unlike the if-else block the compiler read all the blocks sequentially whether the block is true or not.
Syntax
unique if(condition)begin
Statements;
end
else if (condition) begin
Statements;
end
else if (condition) begin
Statements;
end
There are three possibilities to know the working of a unique if block and these are
a. Only one expression is true
If only the expression is true unique if conditional statement will work the same as the basic if else block. The output will be the, set of statements inside the block which is executing.
Example-
The below example shows the three conditional blocks unique if, else if, else if. Here, there are two variables declared one is bit type and the other is int type.
size() is a default function of SV, use to get the size of the given variable. The size of a is 5 and b is 32 (default size if int data type ). So, the size of b is greater than a, which means unique if the conditional expression is true. Then, the compiler jumps from the conditional block code and does not execute other conditional blocks (else if blocks).
Code snippet
bit [4:0] a;
int b;
initial begin
unique if ($size(a)<$size(b))begin //True
$display ("Inside the unique if block");
$display ("The size of a is smaller than b ");
end
else if ($size(a)==$size(b)) begin //False
$display ("Inside the first else if block");
$display ("Size of a = Size of b");
end
else if ($size(a)>$size(b))begin //False
$display ("Inside the second else if block");
$display ("Size of a is greater than the size of b ");
end
$display ("Out from conditional block ");
end
output Snap
The below figure shows the output of the unique if for only one true condition.
fig -5: output: unique if - only one true condition
GitHub Lab Code link:- https://github.com/muneeb-mbytes/SystemVerilog_Course/blob/b7_Team_SiliconCrew/conditional_statement/if_variants/unique_if/unique_if1/unique_if1.sv
GitHub Lab Outputlink:- https://github.com/muneeb-mbytes/SystemVerilog_Course/blob/b7_Team_SiliconCrew/conditional_statement/if_variants/unique_if/unique_if1/unique_if1_log.log
b. None of the conditions is true
**with else **- else block statements execute.
fig -6:flow chart: with else unique if
Example -
The below example shows the execution of a set of statements inside the else block.
Here, the variable is money, and the value assigned to the variable is 900. First conditional statements unique if will be false because money is less than 1000. Then, the compiler will check the else if condition, and again condition becomes false. Then, the compiler at last will execute the else block.
The output will be the set of statements inside the else block.
Code snippet
int money;
initial begin
money = 900;
$display ("Money in account = %0d",money);
$display ("------------------------");
unique if (money>1000)begin //false
$display ("Inside the unique if block ");
$display ("can withdraw money ");
end
else if (money==0)begin //false
$display ("Inside the first else if block ");
$display ("Account block .");
end
else
$display ("Money withdrawal not allowed .");
$display ("--------------------------------");
$display ("Out of the conditional block ");
end
Output snap
The below figure shows the output of the unique if -none of the conditions is true with else.
fig -6: output - unique if -none of the conditions is true with else
GitHub Lab Code link:- https://github.com/muneeb-mbytes/SystemVerilog_Course/blob/b7_Team_SiliconCrew/conditional_statement/if_variants/unique_if/unique_if4/unique_if4.sv
GitHub Lab Output link:- https://github.com/muneeb-mbytes/SystemVerilog_Course/blob/b7_Team_SiliconCrew/conditional_statement/if_variants/unique_if/unique_if4/unique_if4_log.log
without else - The compiler will read all the conditional blocks and gives a warning.
Flow chart - Refer fig -4.
Example-
The below example shows execute of code with the else block.
Here, the variable is a and the value assigned to it is 13. Now, the compiler will check the condition sequentially. First, the unique if conditional expression will be checked. As (a %2) is not equal to 0 so, this conditional expression becomes false. Then, the compiler will go to first else if block and as (a>2) again the conditional expression becomes false. Then, the compiler will check for the next else if block and as a is not equal to 13 again condition becomes false. At last, the compiler will jump from the conditional block and executes the statements outside the conditional blocks.
Code Snippet
initial begin
a =13;
$display ("The value of a = %0d", a);
$display ("------------------------");
unique if (a%2 == 0)begin // false
$display ("Inside the unique if block ");
$display ("a is an even number");
end
else if (a <2)begin // false
$display (" Inside the else if block ");
$display ("a is smaller than 2 ");
end
else if (a !=13) begin // False
$display ("Inside the second else if block ");
$display ("a is not equal to 13 ");
end
$display ("Out of the conditional block ");
end
Output Snap
The below figure shows the output of the unique if -none of the conditions is true without else.
fig -7: output - unique if -none of the conditions is true without else
GitHub Lab Code Link:- https://github.com/muneeb-mbytes/SystemVerilog_Course/blob/b7_Team_SiliconCrew/conditional_statement/if_variants/unique_if/unique_if3/unique_if3.sv
GitHub Lab Output Link:- https://github.com/muneeb-mbytes/SystemVerilog_Course/blob/b7_Team_SiliconCrew/conditional_statement/if_variants/unique_if/unique_if3/unique_if3_log.log
c. More than one condition is true
The compiler read all conditional blocks sequentially whether the expression is true or not. If more than one conditional block is valid, the output compiler executes the statements which are inside the first valid block. The output will be the set of statements inside the first true conditional block that also gives a warning.
Example - Here the variable declaration is "a" and value assigned to it is 12. The compiler will check the first condition, as (a%2==0) is true and then the compiler will execute the unique if conditional block statements. But, here the compiler task is not finished yet. The compiler will go to the next conditional blocks and will check the conditional expression. As both else, if the conditional statement is true because a >0 and a = 12. After that, the compiler will come out from the conditional blocks and executes the statements from the conditional block.
The output will be the set of statements of unique if block and one warning are also there.
Code snippet
bit [3:0] a;
initial begin
a = 12;
$display ("The value of a = %0d", a);
$display ("------------------------");
unique if (a%2 ==0)begin
$display ("Inside the unique if block ");
$display ("a is an even number.");
end
else if (a>0)begin
$display ("Inside the first else if block ");
$display ("a is a positive number");
end
else if (a ==12)begin
$display ("Inside the second else if block ");
$display ("Value of a =12");
end
$display ("Out from the conditional blocks");
$display ("---------------------------------");
end
Output Snap
The below figure shows the output of the unique if -more than the conditions is true.
fig -8: Output - unique if -more than one condition is true
GitHub Lab Code link:- https://github.com/muneeb-mbytes/SystemVerilog_Course/blob/b7_Team_SiliconCrew/conditional_statement/if_variants/unique_if/unique_if2/unique_if2.sv
GitHub Lab Output link:- https://github.com/muneeb-mbytes/SystemVerilog_Course/blob/b7_Team_SiliconCrew/conditional_statement/if_variants/unique_if/unique_if2/unique_if2_log.log
5.unique0if
fig -7 :flow chart: unique0_if
Unique0if is the same as unique if but unlike unique if does not report a violation if none of the conditions is true. unique0if is not synthesizable because it does not display a warning in the output, so the programmer can't be able to read the dead code or the error in the code properly.
Syntax
unique0if(condition)begin
Statements;
end
else if (condition) begin
Statements;
end
else if (condition) begin
Statements;
end
Example -
The below example show the working of unique if condition.
Here, the variable declared is age and the value assigned to it is 17. The compiler will check all the conditional expression and as we can see all the conditional expression is false. So, as the output, after simulation, there will be a set of statements which are out from the conditional block.
Code Snippet
int age;
initial begin
age = 17;
$display ("The age of the person = %0d ",age);
$display ("----------------------------------");
unique0 if(age >18)begin // false
$display ("Inside the unique 0 if block ");
$display ("Eligible for voting");
end
else if(age>30) begin //false
$display ("Inside the first else if block ");
$display ("Eligible as candidate for PM election in India ");
end
else if(age ==10)begin // false
$display ("Inside the second else if block ");
$display ("Wait for 8 years more. ");
end
$display ("Out from the conditional block ");
end
Output Snap
The below figure shows the output of the unique0 if -none of the conditions is true.
fig-9 : Output-unique0 if
GitHub Lab Code link:- https://github.com/muneeb-mbytes/SystemVerilog_Course/blob/b7_Team_SiliconCrew/conditional_statement/if_variants/unique0_if/unique0_if.sv
GitHub Lab Output link:- https://github.com/muneeb-mbytes/SystemVerilog_Course/blob/b7_Team_SiliconCrew/conditional_statement/if_variants/unique0_if/unique0_if_log.log
6.priority if
fig -8: flow chart: priority if
priority if executes conditions sequentially. It is also the same as if-else conditional statement but there are some differences. The below explanation will give a clear picture of how the priority if block works.
Syntax
priority if (cond_expression)begin
Statements;
end
else if (cond_expression)begin
Statements;
end
-------
else begin //(optional)
Statements ;
end
To get the clarity of working on priority if, three conditions are specified and these are -
a. only one conditional expression is true
When only one condition is true, the priority if block is as same as the if else if ... block.
Example
Here, there are three variables declared a,b, and c. The default size of the int data type is 32 bits and the byte is 8 bits. $bit() is the default function of System Verilog which will give the size of the variable. The value assign to a=10 ,b=12 and c =13. First, the priority if the block expression is false because the value of a is not equal to the size of a (12 != 32) and then the compiler will check the next statement. The first else if the condition is true because both a and c are of the same data type.
As the output, the execution of statements inside the first else if block.
It is just the same as the if else if block.
Code Snippet
int a;
byte b;
int c;
initial begin
$display ("The default size of a = ",$bits(a));
$display ("The default size of b = ",$bits(b));
$display ("The default size of c = ",$bits(c));
$display ("-----------------------------------");
a = 10; //assign value
b= 12; // assign value
c=13; // assign value
priority if (a == $bits(a))begin //false
$display ("Inside the priority if block");
$display ("Here , value assign to a = default size of a ");
end
else if ($bits(a)== $bits(c))begin //true
$display ("Inside the first else if block ");
$display ( " Default size of a = default size of c ");
end
else if (a>b)begin //false
$display ("Inside the second else if block ");
$display ("value of a is greater than b ");
end
$display ("-----------------------------");
$display ("Out from the block ");
end
Output Snap
The below figure shows the output of the priority if - only one condition is true.
fig -10:Output-priority if -only one condition is true
GitHub Lab Code link:- https://github.com/muneeb-mbytes/SystemVerilog_Course/blob/b7_Team_SiliconCrew/conditional_statement/if_variants/priority_if/priorityif_1/priorityif_1.sv
GitHub Lab Output link:- https://github.com/muneeb-mbytes/SystemVerilog_Course/blob/b7_Team_SiliconCrew/conditional_statement/if_variants/priority_if/priorityif_1/priorityif_1_log.log
b. More than one conditional expression is true
The compiler will check the conditional expression sequentially. It will execute all the statements and after simulation, the output will be a set of statements inside the first true conditional block with no warning.
Example - Here, the variable is a,b and c, and the value assigned to it is 10,20 and 30. We can see the first conditional expression a>b is false. Then, the compiler will check the next block. First and second else if block both have true conditional expression. But, the compiler only checks the first true expression, executes it, and comes out from the conditional block. The output will be the set of statements inside the first true else if blocked with no warning.
Code Snap
int a,b,c;
initial begin
a = 10;
b =20;
c = 30;
$display ( "The value of a =%0d b = %0d c = %0d ", a,b,c);
$display ("-----------------------------------------------");
priority if (a>b)begin //false
$display ("Inside the priority if block ");
$display (" a <b");
end
else if ( b <c )begin //true
$display ("Inside the first else if block");
$display ("b<c");
end
else if (a <c )begin //true
$display ("Inside the second else if block ");
$display ( "a < c ");
end
$display ("Out from the conditional block ");
end
Output Snap
The below figure shows the output of the priority if - more than one condition is true.
fig -11: Output -priority if -more than one true condition
GitHub Lab Code link:- https://github.com/muneeb-mbytes/SystemVerilog_Course/blob/b7_Team_SiliconCrew/conditional_statement/if_variants/priority_if/priorityif_2/priorityif_2.sv
GitHub Lab Output link:- https://github.com/muneeb-mbytes/SystemVerilog_Course/blob/b7_Team_SiliconCrew/conditional_statement/if_variants/priority_if/priorityif_2/priorityif_2_log.log
c.none of the condition is true
c1. without else
When none of the conditional expressions is true, the compiler will come out from the conditional blocks and execute the statements which are out from the conditional block and display a warning.
Example -
Here, there are three conditional expressions. The compiler checks the conditional expression because all are false. Then, the output will be the set of statements out from the block and display a warning.
Code Snippet
int bill;
initial begin
bill = 6000; // assign the value
$display ("Total bill = %0d",bill);
$display ("------------------------");
priority if (bill < 1000)begin // false
$display ("Inside the priority if ")
$display ("No discount");
end
else if (bill ==8000)begin //false
$display ("Inside the first else if block ");
$display ("10% discount available ");
end
else if (bill >8000)begin // false
$display ("Inside the second else if block ");
$display ("15% discount available");
end
$display ("Out from the conditional block");
$display ("Do more shopping for more discount ......");
end
Output Snap
The below figure shows the output of the priority if - none of the conditions is true without else.
fig -12:Output - priority if -none of the conditions is true without else
GitHub Lab Code link:- https://github.com/muneeb-mbytes/SystemVerilog_Course/blob/b7_Team_SiliconCrew/conditional_statement/if_variants/priority_if/priorityif_3/priorityif_3.sv
GitHub Lab Output link:- https://github.com/muneeb-mbytes/SystemVerilog_Course/blob/b7_Team_SiliconCrew/conditional_statement/if_variants/priority_if/priorityif_3/priorityif_3_log.log
c2.with else
fig -9: flow chart: with else priority if
When none of the conditional expressions is true by default compiler to execute the statements which are inside the else block.
Example -
In the below example, all the conditional expression is false and then the compiler will execute the statements inside the else block.
Code Snippet
int bill;
initial begin
bill = 6000; // assign the value
$display ("Total bill = %0d",bill);
$display ("------------------------");
priority if (bill < 1000)begin // false
$display ("Inside the priority if ");
$display ("No discount");
end
else if (bill ==8000)begin //false
$display ("Inside the first else if block ");
$display ("10 percent discount available ");
end
else if (bill >8000)begin // false
$display ("Inside the second else if block ");
$display ("15 percent discount available");
end
else begin
$display ("Inside the else block ");
$display ("5 percent discount available ");
end
$display ("Out from the conditional block");
$display ("Do more shopping for more discount ......");
end
Output Snap
The below figure shows the output of the priority if - more than one condition is true without else.
fig -13: Output - priority if -none of the conditions is true without else
GitHub Lab Code link:- https://github.com/muneeb-mbytes/SystemVerilog_Course/blob/b7_Team_SiliconCrew/conditional_statement/if_variants/priority_if/priorityif_4/priorityif_4.sv
GitHub Lab Output link:- https://github.com/muneeb-mbytes/SystemVerilog_Course/blob/b7_Team_SiliconCrew/conditional_statement/if_variants/priority_if/priorityif_4/priorityif_4_log.log
Difference between conditional statements
| S.No. | Condition | if elseif | unique if | unique0 if | priority if |
|---|---|---|---|---|---|
| 1. | only one conditional expression is true | execute the set of statements inside the true conditional block | execute the set of statements inside the true conditional block | execute the set of statements inside the true conditional block | execute the set of statements inside the true conditional block |
| 2. | more than one conditional expression is true | executes the first true conditional block statements, no warning display | executes the first true conditional block statements, a warning display | executes the first true conditional block statements, a warning display | executes the first true conditional block statements, no warning display |
| 3. | none of the conditional expressions is true without else | execute the statements out from the conditional block, no warning display | execute the statements out from the conditional block, a warning display | execute the statements out from the conditional block, no warning display | execute the statements out from the conditional block, a warning display |
Purpose of warning
The unique if, unique0 if, and priority if are the updated versions of if-else conditional statements in the system Verilog. These conditional statements display the warning which helps to detect the dead code or unused conditional statements.
Dead code
Dead code is code that doesn’t have any effect on your simulation or synthesis. Examples of dead code are signals that are never used or conditions that are never triggered.
Dead code does not bother the simulator or the synthesis tool. However, it consumes the mental energy of anybody reading the code. People will try to figure out the purpose of a given statement and it may take a while before they realize that they are dealing with a dead code. This makes it more expensive to review code and reuse code. In general, the dead code is a form of technical debt that should be avoided.
case
The case statement allows us to execute the code for the particular case expression. This will give the proper structure for a long code and decrease the complexity of the code also.
A case statement evaluates a given expression and based on the evaluated value(matching a certain condition), it executes the statements associated with it. Basically, it is used to perform different actions based on different conditions.
A system Verilog case statement starts with the case keyword and ends with the endcase keyword. A block of multiple statements must be grouped within the begin and end statements.
Flowchart:
Fig -10: flow chart: case statement with default statement
Syntax:
case(condition)
condition_1: Statements ;
condition_2: Statements ;
...........
conditon_N: Statements;
default : Statements;
endcase
case statement in which no conditions are true
Example:
x = 2'b11;
case(x)
00 : $display("Value of x = %0b", x);
01 : $display("Value of x = %0b",x);
10 : $display("Value of x = %0b",x);
//11 : $display("Value of x = %0b" ,x);
default : $display("Value of x is not found");
endcase
In the above example, here expression= "x" should match one of the case items but here no condition is true. In this '11' value is given to the x so the case item '11' is not matched with the expression = 'x'. Then default get executes. If none of the conditions is true then the default statement gets executed. This will display 'Value of x is not found' in the output.
Output Snap:
The below figure shows the output of the case statement in which one condition is true.
Fig -14: Output: case statement in which one condition is true
In the above output, the case statement will execute for all conditions and be true for one of the conditions. This will print the Value of x = 1 in the output.
GitHub Lab Code link :- https://github.com/muneeb-mbytes/SystemVerilog_Course/blob/b7_Team_SiliconCrew/conditional_statement/case_variants/case/case.sv
GitHub Lab Output link :- https://github.com/muneeb-mbytes/SystemVerilog_Course/blob/b7_Team_SiliconCrew/conditional_statement/case_variants/case/case_op.log
Using of Case statement without a default
In case statements, the default statement is used. The default statement is optional, and there can be only one default statement in a case statement.
If none of the given case conditions is true, the statement within the default statement is executed.
Execution will exit the case block without doing anything if none of the items matches the condition and a default statement is not given.
Flowchart:
Fig -11: flow chart: case statement without default statement
Syntax:
case(condition)
condition_1: Statements ;
condition_2: Statements ;
...........
conditon_N: Statements;
endcase
Example:
x = 2'b01;
case(x)
00 : $display("Value of x = %0b", x);
01 : $display("Value of x = %0b",x);
10 : $display("Value of x = %0b",x);
11 : $display("Value of x = %0b" ,x);
endcase
In the above example, a case statement is used without the default statement. A default statement is used when none of the conditions is true. In this one of the conditions is true and it will print that the value of x as '1'
In this example, if none of the case conditions is true or no default statement is not given then execution will exit the case block without doing anything
Output Snap:
The below figure shows the output of the case statement without using the default statement.
Fig -15: Output: case statement in which one condition is true
In the above output, the case statement is used without a default statement. In this one case condition is true, at the time of execution the output will come to 'Value of x = 1'.If none of the conditions is true or the default statement is not given then the execution will exit the case block without anything.
GitHub Lab Code link https://github.com/muneeb-mbytes/SystemVerilog_Course/blob/b7_Team_SiliconCrew/conditional_statement/case_variants/case_default/case_without_default.sv
GitHub Lab output link https://github.com/muneeb-mbytes/SystemVerilog_Course/blob/b7_Team_SiliconCrew/conditional_statement/case_variants/case_default/case_without_default_op.log
Using of range in case statement with the use of inside statement:
In this, the range is declared in the case statement with the use of an inside statement.
If we want to give a range value in a case statement, this will be done with help of an inside statement.
Syntax:
case(condition) inside
condition_1_[a:b]: Statements ;
condition_2:_[c:d] Statements ;
...........
conditon_N_[y:z]: Statements;
endcase
Example:
case(x) inside
[2:3] : $display("Value of x = %0d", x);
[4:5] :$display("Value of x = %0d",x);
[6:9] : $display("Value of x = %0d",x);
[8:9] : $display("Value of x = %0d" ,x);
default : $display("Value of x is not found");
endcase
In the above example, we are declaring a range in a case statement with the use of inside statement. In this, they will get the value from the declared range by the use of an inside statement.
Output Snap:
The below figure shows the output of the case statement with a range.
Fig -16: Output: case statement with a range
In the above output, the case statement will get executed with the use of an inside statement. The case statement will get executed and displays the output 'Value of x = 6'
GitHub Lab Code link https://github.com/muneeb-mbytes/SystemVerilog_Course/blob/b7_Team_SiliconCrew/conditional_statement/case_variants/case_range/case_range.sv
GitHub Lab Output link https://github.com/muneeb-mbytes/SystemVerilog_Course/blob/b7_Team_SiliconCrew/conditional_statement/case_variants/case_range/case_range_op.log
Use of Break statement inside the case statement:
The break statement is not allowed to use within the loops. while using a break inside the case statement, an error has occurred.
Syntax
case(condition) inside
condition_1: Statements ;
condition_2: begin
Statements ;
break;
end
...........
conditon_N: Statements;
endcase
Example:
case(x)
00 : $display("Value of x = %0b", x);
01 : begin
$display("Value of x = %0b",x);
break;
end
10 : $display("Value of x = %0b",x);
11 : $display("Value of x = %0b" ,x);
default : $display("Value of x is not find");
endcase
In the above example, here we use a break statement inside the case statement. This will throw an error, i.e. break statement is not allowed within the case statement.
Output Snap:
The below figure shows the output of using a break statement inside the case statement.
Fig - 17: Output: break statement is not allowed inside the case
In the above output, a break statement is used inside the case statement. System Verilog does not allow the use of a break statement inside the case statement.
In this, an error will occur.
GitHub Lab Code link https://github.com/muneeb-mbytes/SystemVerilog_Course/blob/b7_Team_SiliconCrew/conditional_statement/case_variants/break_case/break_case.sv
GitHub Lab Output link https://github.com/muneeb-mbytes/SystemVerilog_Course/blob/b7_Team_SiliconCrew/conditional_statement/case_variants/break_case/break_case_op.log
Using of disable keyword to disable the nested loop inside the task
Using the disable keyword followed by a task will only disable tasks and named blocks. The disable statement discontinues the execution of a named group of statements.
Example:
task nes();
for (int i=1;i<=3;i++)
begin
for(int j=1;j<=3;j++)
begin
if(i==2)
begin
disable nes;
end
$display("\t i= %0d , j= %0d ",i,j);
end
end
endtask
endmodule:nested_loop
In the above example, disable keyword is used to disable the task at a particular iteration. Inside the task, we declared the two nested "for" loops in which we use the if condition to move out from the loops with the use of disable keyword. Inside the task, the 'if' condition has been declared at iteration '2'. At iteration '2' if the condition matches and it will disable the task with the help of disable keyword.
Output Snap
The below figure shows the output in which disable keyword is used to disables the task.
Fig - : Output: Using of disable keyword inside the task
GitHub Lab Code link: https://github.com/muneeb-mbytes/SystemVerilog_Course/blob/b7_Team_SiliconCrew/conditional_statement/case_variants/nested_loop_break/nested_loop.sv
GitHub Lab Output Code: https://github.com/muneeb-mbytes/SystemVerilog_Course/blob/b7_Team_SiliconCrew/conditional_statement/case_variants/nested_loop_break/nested_loop_op.log
There are three updates for the case statement in the system Verilog and these are -
- unique case
- unique0 case
- priority case
1. unique case
In a unique case, if all the case condition is false, it will display a warning (no match is found for the case statement ) with no error.
If all the conditions are true or more than one condition is true, it will read the first right or matched case condition and will display the output with one warning and no error.
Syntax :
unique case(condition)
condition_1: Statements ;
condition_2: Statements ;
............
conditon_N: Statements;
endcase
Example:
all the conditions are false-
x = 2'b01;
unique case(x)
00 : $display(" Value of x is = %0b", x);
//01 : $display(" Value of x is = %0b", x);
10 : $display(" Value of x is = %0b", x);
11 : $display(" Value of x is = %0b", x);
endcase
In the above example, the unique case statement is used. Here all the conditions are false, this will print the output with a warning and no error.
Output Snap:
The below figure shows the output of a unique case statement in which no conditions are true.
Fig - 18: Output: In a unique case, no conditions are true
In the above output, all the condition is false so the unique case gives a warning with no error.
GitHub Lab Code link https://github.com/muneeb-mbytes/SystemVerilog_Course/blob/b7_Team_SiliconCrew/conditional_statement/case_variants/unique_case/unique_none_true/unique_case.sv
GitHub Lab Output link https://github.com/muneeb-mbytes/SystemVerilog_Course/blob/b7_Team_SiliconCrew/conditional_statement/case_variants/unique_case/unique_none_true/unique_case_op.log
more than one condition is true
In a unique case, if all the case condition is false, it will display a warning (no match is found for the case statement ) with no error.
If all the conditions are true or more than one condition is true, it will read the first right or matched case condition and will display the output with one warning and no error.
Flowchart:
Fig -12: flow chart: unique case statement
Example:
x = 2'b00;
unique case(x)
00 : $display("Value of x is =%0b" , x);
00 : $display("Value of x is =%0b" , x);
01 : $display("Value of x is =%0b" , x);
10 : $display("Value of x is =%0b" , x);
11 :$display("Value of x is =%0b" , x);
endcase
In the above example, a unique case statement is used. In the unique case, if more than one condition is true, it will read the first right or matched case condition and will display the output with one warning and no error.
If these two condition is true, at the time of execution this will take the first matched condition and print the value of x = '0' with a warning(no error)
Output Snap:
The below figure shows the output of a unique case statement in which more than one condition is true.
Fig -19: Output: unique case in which more than one condition is true
In the above output, a unique case statement is used. In this more than one condition is true, the unique case will read the first matched condition and will give the Value of x = '0' with a warning (no error).
GitHub Code Lab link https://github.com/muneeb-mbytes/SystemVerilog_Course/blob/b7_Team_SiliconCrew/conditional_statement/case_variants/unique_case/unique_case_default/unique_case_default.sv
GitHub Lab Output link https://github.com/muneeb-mbytes/SystemVerilog_Course/blob/b7_Team_SiliconCrew/conditional_statement/case_variants/unique_case/unique_case_default/unique_case_default_op.log
unique case with default statement
In this, we will use the default statement inside the unique case statement.
If none of the conditions is true inside the unique case statement then the default statement will get executed.
Flowchart:
Fig -13: flow chart: unique case with default statement
Syntax:
unique case(condition)
condition_1: Statements ;
condition_2: Statements ;
............
conditon_N: Statements;
default : Statements;
endcase
Example:
x = 2'b01;
unique case(x)
00 : $display("Value of x is =%0b" , x);
// 01 : $display("Value of x is =%0b" , x);
10 : $display("Value of x is =%0b" , x);
11 : $display("Value of x is =%0b" , x);
default :$display("Value of x is =%0b" , x);
endcase
In the above example, the default statement is used inside the unique case statement.
In this, if no conditions of the case statement are true then the default statement will get executed.
Output Snap:
The below figure shows the output of a unique case statement by using the default statement.
Fig - 20: Output: no conditions are true, default statement gets executed
In the above output, there is no condition is true inside the case statement, then the default statement is get executed and prints the 'Value of x = 1' in the output.
GitHub Code Lab link https://github.com/muneeb-mbytes/SystemVerilog_Course/blob/b7_Team_SiliconCrew/conditional_statement/case_variants/unique_case/unique_case_default/unique_case_default.sv
GitHub Lab Output link https://github.com/muneeb-mbytes/SystemVerilog_Course/blob/b7_Team_SiliconCrew/conditional_statement/case_variants/unique_case/unique_case_default/unique_case_default_op.log
2. uniuqe0 case
In the unique0 case, if all the case condition is false, it will not display a warning with no error.
If all the conditions are true or more than one condition is true, it will read the first right or matched case condition and will display the output with one warning and no error.
Syntax :
unique0 case(condition)
condition_1: Statements ;
condition_2: Statements ;
...........
conditon_N: Statements;
endcase
Example:
x = 2'b01;
unique0 case(x)
00 : $display(" Value of x is = %0b", x);
01 : $display(" Value of x is = %0b", x);
10 : $display(" Value of x is = %0b", x);
11 : $display(" Value of x is = %0b", x);
01 : $display(" Value of x is = %0b", x);
endcase
In the above example, the unique0 case is used. In these two conditions is true and unique0 will read the first right or matched condition and print the output Value of x = "1" with the warning.
Output Snap:
The below figure shows the output of the unique0 case statement in which two conditions are true.
Fig -21: Output: unique0 case in which two conditions are true
In the above output, two conditions are true at a time this will make the case statement not unique, uniquq0 will read the first right matched condition and display the Value of x is 1 with the warning
GitHub Code Lab link https://github.com/muneeb-mbytes/SystemVerilog_Course/blob/b7_Team_SiliconCrew/conditional_statement/case_variants/unique0_case/unique0_case.sv
GitHub Lab Output link https://github.com/muneeb-mbytes/SystemVerilog_Course/blob/b7_Team_SiliconCrew/conditional_statement/case_variants/unique0_case/unique0_case_op.log
3. priority case
In this type of case statement, if more than one case condition is true, it will display the output without giving any error with no warning.
Flowchart:
Fig -14: flow chart: priority case statement
Syntax:
priority case(condition)
condition_1: Statements ;
condition_2: Statements ;
...........
conditon_N: Statements;
endcase
Example:
pqr = 5;
priority case (pqr)
5 : $display ("Found to be 5");
5 : $display ("Again found to be 5");
7 : $display ("Found to be 7");
endcase
In the above example, the priority case is used. In these two conditions is the right or matched condition so the priority case will read the first right condition and execute it and display the output with no warning and no error.
Output Snap:
The below figure shows the output of the priority case statement in which two conditions are true.
Fig -22: Output: priority case statement in which two conditions are true
In the above output, more than one condition is true. priority case checks the first right matched condition, executes it, and displays the output without warning and error.
GitHub Code Lab link https://github.com/muneeb-mbytes/SystemVerilog_Course/blob/b7_Team_SiliconCrew/conditional_statement/case_variants/priority_case/priority_case.sv
GitHub Lab Output link https://github.com/muneeb-mbytes/SystemVerilog_Course/blob/b7_Team_SiliconCrew/conditional_statement/case_variants/priority_case/priority_case_op.log
break
A break statement is used to terminate the loop immediately. When a break statement is encountered inside a loop, the loop iteration stops there. Generally, we use break after giving the condition in code using the if statement.
We can use break statements in any loop(for, foreach, forever, do-while, while, do-while,), for terminating the execution of a loop. It is always used inside the loop. The break statement ends the loop immediately when it is encountered.
Flowchart:
Fig-:15 flow chart: break statement
Syntax:
break;
Example:
foreach(array[i])
if(i==2)begin
$display("----Calling break----");
break;
end
In the above example, a break statement is used inside the loop which terminates the loop when condition is true. In this break is used at index 2 so that the loop stops at index 2 and comes out of the loop.
Output Snap:
The below figure shows the output of using the break statement.
Fig -23 : Output: break statement gets executed at iteration 2
In the above output, a break statement is used inside the loop. The output shows the value for index 0 & 1, after this break statement is encountered and display "Calling break"
GitHub Lab Code link https://github.com/muneeb-mbytes/SystemVerilog_Course/blob/b7_Team_SiliconCrew/break_continue/break/break.sv
GitHub Lab Output link https://github.com/muneeb-mbytes/SystemVerilog_Course/blob/b7_Team_SiliconCrew/break_continue/break/break_op.log
continue:
The continue statement is used to skip the current iteration of a loop. We can use the continue statement inside any type of loop such as for, while, and do-while loop. Basically, continue statements are used in situations when we want to continue the loop but do not want the particular iteration in the loop.
Using continue, we can skip the current iteration of a loop and jumps to the next iteration of the loop immediately
Flowchart:
Fig - 16: flow chart: continue statement
Syntax:
continue;
Example:
foreach(array[i])
begin
if(i==2)begin
$display("-----Calling Continue----");
continue;
end
In the above example, continue statement is used inside the loop that skips the current iteration of a loop. In the following loop continue is used at index 2 so that the loop skips the particular iteration at index 2 and goes for the next iteration.
Output Snap:
The below figure shows the output of using the continue statement.
Fig -24 : Output: continue statement executes at iteration 2
In the above output, the continue statement is used inside the loop. The output shows the value for iterations 0 & 1 and for iteration 2 continue statement is encountered and displays "Calling continue" and after this jumps to the next iteration immediately and prints the value for iterations 3 & 4
GitHub Lab Code link https://github.com/muneeb-mbytes/SystemVerilog_Course/blob/b7_Team_SiliconCrew/break_continue/continue/continue.sv
GitHub Lab output link https://github.com/muneeb-mbytes/SystemVerilog_Course/blob/b7_Team_SiliconCrew/break_continue/continue/continue_sv_op.log