05.Operators - vineethkumarv/SystemVerilog_Course GitHub Wiki

Operators :
the operator is a character that represents a specific mathematical or logical action or process.

                     Figure.1 operators 

We use arithmetic operators to perform basic mathematic functions on our variables. These operators should already be familiar as they are mostly replications of common mathematic symbols.

The table below shows the full list of arithmetic operators in SystemVerilog.

The below figure shows the output of the Arithmetic operator screenshot

                   Figure.2. the output of the arithmetic operator. 

for Better understanding go through this code
GitHub lab code link: https://github.com/muneeb-mbytes/SystemVerilog_Course/blob/b7_Team_SiliconCrew/operators/arithmetic/arithmetic_code.sv

GitHub lab output link: https://github.com/muneeb-mbytes/SystemVerilog_Course/blob/b7_Team_SiliconCrew/operators/arithmetic/arithmetic_code_output.log

Relation operator cheat sheet

These operators compare operands and result in a 1-bit scalar Boolean value.

• 0 if the relation is false
• 1 if the relation is true
• x if any of the operands has unknown x bits

Example:
Consider, a = 111
b = 101

• a < b:Here a is greater than b, the relation is false, so the result is 0.

• a > b:Here a is greater than b, the relation is true, so the result is 1.

• a <= b:Here a is greater than b, the relation is false, so the result is 0.

• a >= b:Here a is greater than b, the relation is true, so the result is 1.

          Figure.3. the output of the relation operator. 

GitHub lab code link https://github.com/muneeb-mbytes/SystemVerilog_Course/blob/b7_Team_SiliconCrew/operators/relational/relational_code.sv

GitHub lab output link https://github.com/muneeb-mbytes/SystemVerilog_Course/blob/b7_Team_SiliconCrew/operators/relational/relational_code_output.log

The equality operators are used to compare expressions. If the comparison fails, then the result will be 0, otherwise, it will be 1. There are two types of Equality operators.

• Case Equality
• Logical Equality.

Equality operator cheat sheet

• If both operands of logical equality (==) or logical inequality (!=) contain unknown (x) or a high-impedance (z) value, then the result of the comparison will be unknown (x). Otherwise, it will be true or false.

• If operands of case equality (===) or case inequality (!==) contain unknown (x) or a high-impedance (z) value, then the result will be calculated bit by bit.

Example:
Consider, a = 111
b = 101

• a == b: Here we perform the logical equality of a,b, the result is zero when both numbers are the same then the result is 1.
• a != b: Here we perform the logical inequality of a,b the result is 1 when both numbers are the same then the result is 0.
• a === b: Here we perform the case equality of a,b the result is zero when both numbers are the same then the result is 1.
• a!=== b: Here we perform the case inequality of a,b the result is 1 when both numbers are the same then the result is 0.

               Figure.4. the output of the equality operator. 

GitHub lab code link https://github.com/muneeb-mbytes/SystemVerilog_Course/blob/b7_Team_SiliconCrew/operators/equality/equality_code.sv

GitHub lab output link https://github.com/muneeb-mbytes/SystemVerilog_Course/blob/b7_Team_SiliconCrew/operators/equality/equality_code_output.log

The Logical operators are similar to the bit-wise operators

In the Logical Operator, these expressions return either a 1 (true) or 0 (false).

There are only three logical operators for better understanding follow the below cheat sheet

Logical operator cheat sheet

Example:
Consider, a = 100
b = 111

• a && b: Here we performing the Logical AND of a,b, and the result is 1.
  when any one of the variable values is zero then the result is 0. and when one of the variable values is 1's then the result is 1.
• a || b: Here we performing the Logical OR of a,b, and the result is 1.
  if all the variable's values are zero then only the result is 0. and if any one of the variable values is 1's then the result is 1.
• **!a **: Here we performing the Logical Not of a and the result is 0. if all variable value is zero then the result is 0. ( just vice versa).

          Figure.5. the output of the Logical operator.  

GitHub lab code link https://github.com/muneeb-mbytes/SystemVerilog_Course/blob/b7_Team_SiliconCrew/operators/logic/logic_code.sv

GitHub lab output link https://github.com/muneeb-mbytes/SystemVerilog_Course/blob/b7_Team_SiliconCrew/operators/logic/logic_code_output.log

Bitwise operators perform a bit-wise operation on two operands.
They take each bit in one operand and perform the operation with the corresponding bit in the other operand. If one operand is shorter than the other, it will be extended on the left side with zeroes to match the length of the longer operand.

Bitwise operator cheat sheet

Example:
Consider, a = 100
b=110

• a & b: bit-wise and of a,b the result is 100.
• a | b: bit-wise or of a,b the result is 110.
• a ~& b: bit-wise nand of a,b the result is 011.
• a ~| b: bit-wise nor of a,b the result is 001.
• a ^ b: bit-wise xor of a,b the result is 101.
• a ~^ b: bit-wise nxor of a,b the result is 010.

                     Figure.6. the output of the Bitwise operator. 

GitHub lab code link https://github.com/muneeb-mbytes/SystemVerilog_Course/blob/b7_Team_SiliconCrew/operators/bitwise/bitwise_code.sv

GitHub lab output link https://github.com/muneeb-mbytes/SystemVerilog_Course/blob/b7_Team_SiliconCrew/operators/bitwise/bitwise_code_output.log

There 2 types of shift operators

• Logical shift operators
• Arithmetic shift operators

Shift operator cheat sheet

The shift operator actually requires two arguments. The first of these is the name of the signal which we want to shift. The second argument is the number of bits we want to shift.

When we use the logical shift operators, all the blank positions are filled with 0's after the signal has been shifted by the required number of bits.

Example:
Consider, a = 101

• a <<1: a is Logical shifted to the left by a 1-bit position and the result is 010.
• a >>1: a is Logical shifted to the right by a 1-bit position and the result is 010.
• a <<<2: a is shifted to the left by a 2-bit position and the result is 100.
• a >>>2: a is Arithmetic shifted to the right by a 2-bit position and when we use unsigned data type in the code, then Arithmetic right will take shifted 2 - bit position and filled with 0's. and the result is 001.
• a >>>2: a is Arithmetic shifted to the right by a 2-bit position. when we use signed data type in the code, then Arithmetic right will take shifted 2- bit position and filled with 1's. and the result is 111.

                 Figure.7. the output of the shift operator.   

GitHub lab code link https://github.com/muneeb-mbytes/SystemVerilog_Course/blob/b7_Team_SiliconCrew/operators/shift/shift_code.sv

GitHub lab output link https://github.com/muneeb-mbytes/SystemVerilog_Course/blob/b7_Team_SiliconCrew/operators/shift/shift_code_output.log

To use the conditional operator, we write a logical expression before the? the operator which is then evaluated to see if it is true or false. The output is assigned to one of two values depending on whether the expression is true or false.

the general syntax for the conditional operator.

output = ? :

Example:
Consider, y = enable ? data1 : data2

In the above example enable condition is true it will execute the data otherwise it going to the data2.

           Figure.8. the output of the Condition operator.   

GitHub lab code link https://github.com/muneeb-mbytes/SystemVerilog_Course/blob/b7_Team_SiliconCrew/operators/conditional/conditional_code.sv

GitHub lab output link https://github.com/muneeb-mbytes/SystemVerilog_Course/blob/b7_Team_SiliconCrew/operators/conditional/conditional_code_output.log

Reduction operators are unary.
They perform a bit-wise operation on a single operand to produce a single-bit result.

Reduction operator cheat sheet

Example:
Consider, a = 1010

• &a: Here we performing the Reduction and operation, and the result is 0.
• |a: Here we performing the Reduction or operation, and the result is 1.
• ~&a: Here we performing the Reduction NAND operation, and the result is 1.
• ~|a: Here we performing the Reduction or operation, and the result is 0.
• ^a: Here we performing the Reduction or operation, and the result is 0.
• ~^a: Here we performing the Reduction or operation, and the result is 1.

         Figure.9. the output of the Reduction operator.

GitHub lab code link https://github.com/muneeb-mbytes/SystemVerilog_Course/blob/b7_Team_SiliconCrew/operators/reduction/reduction_code.sv

GitHub lab output link https://github.com/muneeb-mbytes/SystemVerilog_Course/blob/b7_Team_SiliconCrew/operators/reduction/reduction_code_output.log

Concatenation and Replication operator cheat sheet

• concatenation operator to combine two or more signals into a vector.
  Concatenations are expressed using the brace characters { and },
  with commas separating the expressions within.

**Example: ** a=4'b1010; b=4'b1110; {a,b} -if a and b both are 8-bit numbers, and the results has 8 bits.
Concatenation output is 10101110

Replication Operator
The replication operator is used to replicate a group of bits n times. Say you have a 4-bit variable and you want to replicate it 4 times to get a 16-bit variable.
a=4'b1010; b=4'b1110; {2{a},b} - this is equivalent to {a, a, b} and total number of bit is 12-bit.
Replication Output is 101010101110

           Figure.10. the output of the Concatenation and Replication operator.

GitHub lab code link https://github.com/muneeb-mbytes/SystemVerilog_Course/blob/b7_Team_SiliconCrew/operators/concatenation_Replication/concatenation_code.sv

GitHub lab output link https://github.com/muneeb-mbytes/SystemVerilog_Course/blob/b7_Team_SiliconCrew/operators/concatenation_Replication/concatenation_code_output.log