04.User defined - vineethkumarv/SystemVerilog_Course GitHub Wiki
Typedef used to create new identifiers from longer datatype specification. It is similar to alias command. Typedef uses mainly in complex testbenches in System Verilog because it replaces the longer datatypes like int(unsigned longint, signed shortint), byte ,bit[7:0],logic[7:0] with identifiers in the code. Typedef uses in Class, Structure and Enumeration to make the datatype declarations easier.
Syntax:
typedef <base_type> <size> <type_name>;
The main use of Typedef in class is that sometimes we use class variable before the declaration of the class itself. At that time it will cause some compile errors to the code. So avoid that compile errors , we can use 'typedef class variable' before the declaration of class itself.
Syntax:
typedef class class_name;
Example:
typedef class fruit2;
class fruit1;
fruit2 f;
endclass
class fruit2
fruit1 f;
endclass
Output:
The below figure shows that output of typedef with class.
Fig 1 : Typedef with class
The above example and output shows that how typedef avoids the compiler error in class1 because class2 declaration is not done at that time.
Note: If we didn't use 'typdef class2' at the beginning , it will show some compiler error. It will display the text given inside the $display. The below figure shows the error.
Fig 2 : Error when typedef not used with class.
Github lab code link:https://github.com/muneeb-mbytes/SystemVerilog_Course/blob/b7_team_kachori/data_type/typedef/classtypedef/classtypedef.sv
Github lab output link:https://github.com/muneeb-mbytes/SystemVerilog_Course/blob/b7_team_kachori/data_type/typedef/classtypedef/classtypedef.log
Without Typedef, Structure may happen some compile errors in large complex testbenches. Typedef also provide declarations make more easier.
Syntax:
typedef struct {
datatype name;
datatype name;
}structure_name;
Example:
typedef struct{
string name;
byte id;
longint age;
} personal_ details_s;
Output:
The below figure shows the output of typedef with structure datatype.
Fig 3: Typedef with structure
The above output shows that typedef in structure decreases the usage of longer datatypes by creating new variable. We can see that in example 'longint' datatype changed to 'age' ,it is a new variable that is created by using typedef in structure.
Note : The below figure shows that error when typedef is not used with structure
Fig 4 : Error when typedef is not used with structure.
Github lab code link:https://github.com/muneeb-mbytes/SystemVerilog_Course/blob/b7_team_kachori/data_type/typedef/structtypedef/structtypedef.sv
Github lab output link:https://github.com/muneeb-mbytes/SystemVerilog_Course/blob/b7_team_kachori/data_type/typedef/structtypedef/structtypedef.log
Typedef uses for when we need more than one variable to share the same enumeration values. Without Typedef we will get syntax error. Enumeration datatype create new variable for all values.
Syntax:
typedef enum {
values
} <type_ name>;
Example:
typedef enum {
RORITO,
FLAIRFX,
REYNOLDS
}pen_e;
Output:
The below figure shows the typedef with 'enumeration datatype
Fig 5 : Typedef with Enumeration
The above output shows that enum datatype with typedef .
Note: The below figure shows the error when typedef is not used with enum datatype.
Fig 6 : Error when typedef is not used with enum
If we didn't use typedef with enumeration datatype, it will show syntax error. The output shows that enumeration datatype created a new variable 'e_ pen' and initialize a variable 'pen'. After this, choose one value and assign to 'pen'. It will display the assigned value.
Github lab code link:https://github.com/muneeb-mbytes/SystemVerilog_Course/blob/b7_team_kachori/data_type/typedef/enumtypedef/enumtypedef.sv
Github lab output link:https://github.com/muneeb-mbytes/SystemVerilog_Course/blob/b7_team_kachori/data_type/typedef/enumtypedef/enumtypedef.log