Structure

A structure contains different data types with different sizes which grouped under one single structure name. Structure is originally unpacked form by default, but we can use 'packed' keyword for converting into packed structure. Structure is different from normal array because array uses only same type of elements with sizes whereas structure uses different data types. The unpacked structure declared using 'struct' keyword.

The below figure shows different types of structures in System Verilog.

                                            Fig 1: Structure Diagram  

Types of structure

1.Unpacked structure
2.Packed structure

Unpacked Structure

Unpacked structure is the default structure syntax and is same as normal structure. The different variables holds different data inside the structure known as members of the structure. Structure members were treated as independent variables. when we want to assign values to the members of structure, then use 'structure name. variable'.

Assignments To Struct Members:

structure name = '{value1, value2, value3};

Alternate Method to assign values:

structure name = '{variable1 : value1 , variable2 : value2 , variable 3 : value3};
This method gives initialization done in one step. The variable and value can be separated by a colon '.' .

Syntax:

struct{
list of different types of variables with sizes
} structure name;

Example:

struct{
string name;
bit[15:0] salary;
byte id;
} employee_s;

The below figure shows that the data alignment of unpacked structure.

                                         Fig 2:  Data alignment of unpacked structure     

The 'string' takes 24 bits for "sam" , here string treat as ascii character. Then 16 bits for bit[15:0] and 8 bits for byte. Here bitstream size is 48. Unpacked structure has more memory footprint than packed structure.

Output:

Note: Without using 'Typedef' and if we try to initialize the values line by line using alternate method (Refer Alternate method to assign values), it will show compile error. Without typedef, value initialization can only be done in one line itself.

Fig 3: Compile error when not using typedef

The below output shows the unpacked structure.

                                              Fig 4: Unpacked structure  

The above output illustrates that the unpacked structure contains the different datatypes like string, int, byte etc. The string must be initialised within double quotes only. The variables like int , byte can be assign the value itself.

Github Lab code link: https://github.com/muneeb-mbytes/SystemVerilog_Course/blob/b7_team_kachori/data_type/structure/struct-unpacked/structn.sv

Github Lab output link:https://github.com/muneeb-mbytes/SystemVerilog_Course/blob/b7_team_kachori/data_type/structure/struct-unpacked/structn.log

Packed structure

Packed structure can explicitly done using packed keyword. It stores all members of structures in the form of contiguous form in a specified order. In RTL code, a packed structure is treated as a single vector and each data type in the structure is represented as a bit field. The whole structure is packed together in memory without gaps. Only packed data types like bit , logic and integer data types are also allowed to use in a packed structure.

Note: Structure cannot be packed if it cannot be represented as a vector.

Syntax:

typedef struct packed{
list of different types of variables with sizes
} structure name;

Example:

typedef struct packed{
byte id;
bit[7:0]experience;
logic[15:0]salary;
}employee_ details_s;

The below figure shows that the data alignment of Packed structure.

                                                Fig 5 : Data alignment of Packed structure     

The 'byte' takes 8 bits , 8 bits for bit[7:0] and 16 bits for logic[15:0].Here bitstream size is 32 bit. Packed structure has less footprint than unpacked structure.

Output:

The below output shows that output of packed structure

                                                 Fig 6: Packed structure  

The above output illustrates the output of packed structure. It contains the different datatypes like bit , logic . We can assign values and display as output. Here we cannot use string dataype inside the packed structure because string cannot be treated as single vector. It will show compile error.

Github lab code link :https://github.com/muneeb-mbytes/SystemVerilog_Course/blob/b7_team_kachori/data_type/structure/struct-packed/struct-packed.sv

Github lab output link:https://github.com/muneeb-mbytes/SystemVerilog_Course/blob/b7_team_kachori/data_type/structure/struct-packed/struct-packed.log

Difference of packed structure and Unpacked structure

sr. no.	Packed structure	Unpacked structure
1.	struct packed keyword is used for define packed structure	struct keyword is used for define unpacked structure
2.	Smaller memory footprint because of single bit data declaration	Larger memory footprints because it includes all dataypes
3.	string datatype cannot be used and only packed datatypes and integer dataypes allowed	All datatypes can be used.
4.	It is used in RTL code because it can synthesis the code	It is not used in RTL code because it cannot synthesis by synthesis tool
5.	Entire structure packed together without memory gaps	Unpacked structure doesnot have a packing structure

                                 Table 1: Difference of packed structure and Unpacked structure  

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Union

The union is similar to structures while union shares the memory location. The largest datatype size will be the memory size for all members in the union. The 'union' keyword is used for defined for Union. They are two types: Packed Union and Unpacked Union.

Unpacked Union

The unpacked structure use the keyword 'union' keyword. It uses the datatypes like int, byte ,bit, logic .Only the largest datatype size should be taken for the whole union members. In this scenario, sometimes the whole memory space may not be used for all the union members. The value changed for one variable also effects other members inside the Union.

syntax:

union {
list of elements
} Union_name

Example:

union {
int x;
byte y;
} data_u;

Output:

The below figure shows the output of Unpacked Union.

                                      Fig 1: Output of Unpacked Union.   

The unpacked union contains different datatypes and it should be different size. But the unpacked union shares the memory so, the member which have largest memory size should be same for all union members. Here in example, 'int' and 'byte' datatype is used and 'int' size is 32 bit and 'byte' is 8 bit ,'int' is largest among them so the size of all union members is 32 bit.

Data alignment of Unpacked union

The below figure shows that Data alignment of Unpacked union

                                     Fig 2: Data alignment of Unpacked union       

The figure shows that 'int' takes 32 bit and 'byte' takes 8 bit. But in unpacked union all members share the memory. Here 'int' is the largest datatype, so 32 bits shared for all other members in union.

Github Lab code link:https://github.com/muneeb-mbytes/SystemVerilog_Course/blob/b7_team_kachori/data_type/union/union-unpacked/union-unpack.sv

Github lab output link:https://github.com/muneeb-mbytes/SystemVerilog_Course/blob/b7_team_kachori/data_type/union/union-unpacked/union-unpack.log

Packed Union

The Packed Union is defined by 'union packed' keyword. It uses only same type elements like 'bit' , 'logic', 'reg' with same size. This is one of the limitation of packed Union.

syntax:

typedef union packed {
list of different elements
} Union_name;

Example:

typedef union packed {
bit [7:0];
bit [7:0];
} abc_u ;

Data alignment of packed union

The below figure shows the Data alignment of packed union

                                              Fig 3:  Data alignment of packed union  

The figure shows that bit datatype and 8bit size is used. Inside packed union , all members should be same type of element and same size . Here 8 bit size allocated for all union members.

Output:

The below figure shows that the output of packed union.

                                              Fig 4: Output of packed union.   

The packed union output shows that only same type of element eg, 'bit' and only with same size can be used as union members.

Github Lab code link:https://github.com/muneeb-mbytes/SystemVerilog_Course/blob/b7_team_kachori/data_type/union/union-packed/unionpack.sv

Github lab output link: https://github.com/muneeb-mbytes/SystemVerilog_Course/blob/b7_team_kachori/data_type/union/union-packed/unionpack.log

Difference between structure and union

sr. no.	structure	Union
1.	struct keyword is used to create structure variable	Union keyword is used to define union variable
2.	Handle different types of element at a time	Handle single type of element at a time
3.	Each structure element gets memory separately	Every element share the memory space separately
4.	The value of element doesn't get changed when other elements change.	The element value will get changed when other element value changes
5.	Structure variable size is same or greater than sum of elements	The size of union variable is same as the size of largest dataype

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