01.Data Types - vineethkumarv/SystemVerilog_Course GitHub Wiki

Data Types

In Verilog, all the data types were of 4-state, i.e., it could represent 0, 1, X and Z. However, in the case of test benches, these 4-state variables were not required. For example, to count the number of packets, we would require a 2-state variable. Thus, System Verilog introduces a new class of variables of 2-states, i.e., 0 and 1.

data_type

data type cheat sheet

sr. no. data type
1. 4-state
2. 2-state
3. Arrays
4. Strings
5. Structures and Union
6. Enumerated
7. User defined 
    Tabular column.1. data types

Signed and Unsigned numbers

Unsigned number:The unsigned numbers do not use any flag for the sign, i.e., only positive numbers can be stored by the unsigned numbers.
The range of the unsigned binary numbers starts from 0 to ((2^n) - 1), n represents number of bits.

Signed numbers:The positive and negative values are differentiated by using the sign flag in signed numbers. Signed bit makes two possible representations of zero (positive (0) and negative (1)).
The range of the signed binary numbers starts from -2^(n-1) to 2^(n-1)-1, n represents number of bits.
There are the following types of representation of signed binary numbers:

  1. Sign-Magnitude form In this form, a binary number has a bit for a sign symbol. If this bit is set to 1, the number will be negative else the number will be positive if it is set to 0. Apart from this sign-bit, the n-1 bits represent the magnitude of the number.

  2. 1's Complement By inverting each bit of a number, we can obtain the 1's complement of a number. The negative numbers can be represented in the form of 1's complement. In this form, the binary number also has an extra bit for sign representation as a sign-magnitude form.

  3. 2's Complement By inverting each bit of a number and adding plus 1 to its least significant bit, we can obtain the 2's complement of a number. The negative numbers can also be represented in the form of 2's complement. In this form, the binary number also has an extra bit for sign representation as a sign-magnitude form.

Example to illustrate signed and unsigned number

Consider 3 bit, here n=3,

  • Unsigned range
    0 to (2^(n) - 1
    0 to (2^(3)) - 1
    0 to 7
Unsigned bits Value in decimal
000 0
001 1
010 2
011 3
100 4
101 5
110 6
111 7
  • Signed range
    -2^(n-1) to 2^(n-1)-1
    -2^(3-1) to 2^(3-1)-1
    -2^(2) to 2^(2)-1
    -4 to 3
Signed bits Value in decimal
000 0
001 1
010 2
011 3
100 -4
101 -3
110 -2
111 -1

In the above example, the MSB bit is considered for sign flag, as mentioned earlier, if MSB is 0 means positive and 1 means negative.
For 100, 1 is MSB i.e negative
Take 2's compliment of 00 first, take 1's compliment , 11
add 1, 1
result is 100 i.e 4
so it is -4

4-state data type cheat sheet

sr. no. data type 2-state/4-state bit signed/unsigned
1. reg 4 >=1 unsigned
2. wire 4 >= unsigned
3. logic 4 >=1 unsigned
4. integer 4 32 signed
5. time 4 64 unsigned
6. real 4 64 unsigned 
     Tabular column.2. 4-state data type

Four state

The below tabular column represent the 4 different state.

State Description
0 Logic state 0
1 Logic state 1
x or X Logic state unknown(related to registers)
z or Z Logic state high impedance (related to wires) 
                                      Tabular column.3. value of 4-state

1. reg

A reg variable is used to model storage elements such as latches, flip-flops and memories, it stores a value and it is is used in a procedural assignment.

Syntax : reg variable_name;

2. wire

A wire is a Verilog data-type used to connect elements and to connect nets that are driven by a single gate or continuous assignment.

Syntax : wire variable_name;

tri

The tri net type can be used where multiple drivers drive a net.

3. Logic

The logic data type is a 4 state type that can take values 0,1,x and z. logic data type which can be used in place of both the wire and reg data types because wire data type does not have multiple drivers.
By default logic data type is unsigned and its initial value is x. logic data type can be driven in both procedural block and continuous assign statements.

syntax : logic variable_name;

Example : logic [2:0] logic_data_type;

The below figure shows the output of logic data type.

logic

                                   Figure.1. logic output

Github lab code link: https://github.com/muneeb-mbytes/SystemVerilog_Course/blob/b7_team_kachori/data_type/two_and_four_state/logic/logic_file.sv

Github lab output link: https://github.com/muneeb-mbytes/SystemVerilog_Course/blob/b7_team_kachori/data_type/two_and_four_state/logic/logic_file.log

4. integer

integer is 4-state data type, integer can be either 0,1,x and z which represent a 32-bit signed number. Default value of integer is x. integer can hold values ranging from -2^31 to (2^31)-1.

Syntax : integer variable_name;

Example : integer integer_data;

The below figure shows the output of integer data type.

integer

                                   Figure.2. integer output

Github lab code link: https://github.com/muneeb-mbytes/SystemVerilog_Course/blob/b7_team_kachori/data_type/two_and_four_state/integer_data_type/data_type_integer.sv

Github lab output link: https://github.com/muneeb-mbytes/SystemVerilog_Course/blob/b7_team_kachori/data_type/two_and_four_state/integer_data_type/data_type_integer.log

5. time

time is special data type for simulation time measuring. It is 4-state data type,represent 64-bit unsigned integer, that can be used in conjunction with the $time system task to hold current simulation time.

Syntax : time variable_name;

Example : time time_data;
time_data = $time;

The below figure shows the output of time data type.

time

                                 Figure.3. time output

Github lab code link: https://github.com/muneeb-mbytes/SystemVerilog_Course/blob/b7_team_kachori/data_type/two_and_four_state/time_data_type/data_type_time.sv

Github lab output link: https://github.com/muneeb-mbytes/SystemVerilog_Course/blob/b7_team_kachori/data_type/two_and_four_state/time_data_type/data_type_time.log

6. real

The real data type implemented as a 64-bit real number. Real numbers can be specified in either decimal notation (4.43) or in scientific notation (42e8). Default value of real data type is 0.

Syntax : real variable_name;

Example : real real_data;
real_data = 4.43;

The below figure shows the output of real data type.

real

                                    Figure.4. real output

Github lab code link: https://github.com/muneeb-mbytes/SystemVerilog_Course/blob/b7_team_kachori/data_type/two_and_four_state/real_data_type/data_type_real.sv

Github lab output link: https://github.com/muneeb-mbytes/SystemVerilog_Course/blob/b7_team_kachori/data_type/two_and_four_state/real_data_type/data_type_real.log

2-state data type cheat sheet

sr. no. data type 2-state/4-state bit signed/unsigned
1. bit 2 >=1 unsigned
2. byte 2 8 signed
3. shortint 2 16 signed
4. int 2 32 signed
5. longint 2 64 signed 
     Tabular column.4. 2-state data type

1. bit

bit is 2-state which is used most often test benches. It can be either 0 or 1 which represents a single bit. Default value of bit data type is 0.

Syntax : bit variable_name;

Example : bit single_data;
bit [3:0] multi_bit_data;

The below figure shows the output of bit data type.

bit

                                     Figure.5. bit output

Github lab code link: https://github.com/muneeb-mbytes/SystemVerilog_Course/blob/b7_team_kachori/data_type/two_and_four_state/bit_data_type/data_type_bit.sv

Github lab output link: https://github.com/muneeb-mbytes/SystemVerilog_Course/blob/b7_team_kachori/data_type/two_and_four_state/bit_data_type/data_type_bit.log

2. byte

byte is 2-state data type which is used most often test benches. It can be either 0 or 1 which represent a 8-bit signed integer. Default value of byte is 0.

Syntax : byte variable_name;

Example : byte byte_data;

The below figure shows the output of byte data type.

byte

                              Figure.6. byte output

Github lab code link: https://github.com/muneeb-mbytes/SystemVerilog_Course/blob/b7_team_kachori/data_type/two_and_four_state/byte_data_type/data_type_byte.sv

Github lab output link: https://github.com/muneeb-mbytes/SystemVerilog_Course/blob/b7_team_kachori/data_type/two_and_four_state/byte_data_type/data_type_byte.log

3. shortint

shortint is 2-state data type. It can be either 0 or 1 which represent a 16-bit signed integer. Default value of shortint is 0.

Syntax : shortint variable_name;

Example : shortint shortint_data;

The below figure shows the output of shortint data type.

shortint

                                   Figure.7. shortint output

Github lab code link: https://github.com/muneeb-mbytes/SystemVerilog_Course/blob/b7_team_kachori/data_type/two_and_four_state/shortint_data_type/data_type_shortint.sv

Github lab output link: https://github.com/muneeb-mbytes/SystemVerilog_Course/blob/b7_team_kachori/data_type/two_and_four_state/shortint_data_type/data_type_shortint.log

4. int

int is 2-state data type which is used most often testbenches. It can be either 0 or 1 which represent a 32-bit signed integer. Default value of int is 0.

Syntax : int variable_name;

Example : int int_data;

The below figure shows the output of int data type.

int

                                  Figure.8.int output

Github lab code link: https://github.com/muneeb-mbytes/SystemVerilog_Course/blob/b7_team_kachori/data_type/two_and_four_state/int_data_type/data_type_int.sv

Github lab output link: https://github.com/muneeb-mbytes/SystemVerilog_Course/blob/b7_team_kachori/data_type/two_and_four_state/int_data_type/data_type_int.log

5. longint

longint is 2-state data type. It can be either 0 or 1 which represent a 64-bit signed integer. Default value of longint is 0.

Syntax : longint variable_name;

Example : longint longint_data;

The below figure shows the output of longint data type.

longint

                                    Figure.9. longint output

Github lab code link: https://github.com/muneeb-mbytes/SystemVerilog_Course/blob/b7_team_kachori/data_type/two_and_four_state/longint_data_type/data_type_longint.sv

Github lab output link: https://github.com/muneeb-mbytes/SystemVerilog_Course/blob/b7_team_kachori/data_type/two_and_four_state/longint_data_type/data_type_longint.log

Data type casting

casting means the conversion of one data type to another datatype.

There are two types of casting,

  • Static casting
  • Dynamic casting

static casting : The casting happens at compile time. So, there will not be any run time error. static casting is only applicable to fixed data types. It does not apply to the Object-Oriented programming concept.

Syntax :

data_type'(variable or expression or value);

dynamic casting : Casting happens at run-time. If the casting is invalid, an error is reported. Dynamic casting is used to cast the assigned values to the variables that might not be ordinarily valid. The $cast is the system method. The $cast can be either function or task.

Syntax :

$cast(destination_variable, source_expression_or_variable);

static casting

1. integer to int

Example : int_data = int'(integer_data);

The below figure shows the output of integer to int casting.

integer_to_int

                                   Figure.10. integer to int casting output

Github lab code link: https://github.com/muneeb-mbytes/SystemVerilog_Course/blob/b7_team_kachori/data_type/casting_data_type/integer_to_int/integer_to_int.sv

Github lab output link: https://github.com/muneeb-mbytes/SystemVerilog_Course/blob/b7_team_kachori/data_type/casting_data_type/integer_to_int/integer_to_int.log

2. shortint to int and longint

Example : int_data = int'(shortint_data);
longint_data = longint'(shortint_data);

The below figure shows the output of shortint to int and shortint to longint casting.

shortint_to_i_l

                                   Figure.11. shortint to int and shortint to longint casting output

Github lab code link: https://github.com/muneeb-mbytes/SystemVerilog_Course/blob/b7_team_kachori/data_type/casting_data_type/shortint/shortint_casting.sv

Github lab output link: https://github.com/muneeb-mbytes/SystemVerilog_Course/blob/b7_team_kachori/data_type/casting_data_type/shortint/shortint_casting.log

3. int to longint

Example : longint_data = longint'(int_data);

The below figure shows the output of int to longint casting.

int_to_longint

                                   Figure.12. int to longint casting output

Github lab code link: https://github.com/muneeb-mbytes/SystemVerilog_Course/blob/b7_team_kachori/data_type/casting_data_type/int_to_longint/int_to_longint.sv

Github lab output link: https://github.com/muneeb-mbytes/SystemVerilog_Course/blob/b7_team_kachori/data_type/casting_data_type/int_to_longint/int_to_longint.log

4. real to int

Example : int_data = int'(real_data);

The below figure shows the output of real to int casting.

real_to_int

                                   Figure.13. real to int casting output

Github lab code link: https://github.com/muneeb-mbytes/SystemVerilog_Course/blob/b7_team_kachori/data_type/casting_data_type/real_to_int/real_to_int.sv

Github lab output link: https://github.com/muneeb-mbytes/SystemVerilog_Course/blob/b7_team_kachori/data_type/casting_data_type/real_to_int/real_to_int.log

5. real to time

Example : time_data = time'(real_data);

The below figure shows the output of real to time casting.

real_to_time

                                   Figure.14. real to time casting output

Github lab code link: https://github.com/muneeb-mbytes/SystemVerilog_Course/blob/b7_team_kachori/data_type/casting_data_type/real_to_time/real_to_time.sv

Github lab output link: https://github.com/muneeb-mbytes/SystemVerilog_Course/blob/b7_team_kachori/data_type/casting_data_type/real_to_time/real_to_time.log

6. logic to byte

Example : byte_data = byte'(logic_data);

The below figure shows the output of logic to byte casting.

logic_to_byte

                                   Figure.15. logic to byte casting output

Github lab code link: https://github.com/muneeb-mbytes/SystemVerilog_Course/blob/b7_team_kachori/data_type/casting_data_type/logic_to_byte/logic_to_byte.sv

Github lab output link: https://github.com/muneeb-mbytes/SystemVerilog_Course/blob/b7_team_kachori/data_type/casting_data_type/logic_to_byte/logic_to_byte.log

7. bit to byte

Example : byte_data = byte'(bit_data);

The below figure shows the output of bit to byte casting.

bit_to_byte

                                   Figure.16. bit to byte casting output

Github lab code link: https://github.com/muneeb-mbytes/SystemVerilog_Course/blob/b7_team_kachori/data_type/casting_data_type/bit_to_byte/bit_to_byte.sv

Github lab output link: https://github.com/muneeb-mbytes/SystemVerilog_Course/blob/b7_team_kachori/data_type/casting_data_type/bit_to_byte/bit_ti_byte.log

enum

Enumerated data types defines a set of named values.

Syntax : enum enum_base_type(optional) {
<enum_name_declaration> = constant_expr(optional)...
}<enum_type_identifier>;

Example : enum {MONDAY,
TUESDAY,
WEDNESDAY,
THURSDAY,
FRIDAY,
SATURDAY,
SUNDAY
} days;

  • An enumerated type is stored as type β€˜int’ unless specified as something else.
  • This type automatically gives a unique value to every name in the list.
  • Values default to the β€˜int’ type starting at 0 and then incrementing by 1.
  • If a value is not specified for a name, it gets the value of the previous name in the list incremented by 1.

In the below figure output of default value of enum.

default_value

                               Figure.17. Output of enum default value

Github lab code link: https://github.com/muneeb-mbytes/SystemVerilog_Course/blob/b7_team_kachori/data_type/two_and_four_state/enum_data_type/default_value_enum/default_value_enum.sv

Github lab output link: https://github.com/muneeb-mbytes/SystemVerilog_Course/blob/b7_team_kachori/data_type/two_and_four_state/enum_data_type/default_value_enum/default_value_enum.log

In the below figure output of set value of enum.

set_value

                               Figure.18. Output of set enum value

Github lab code link: https://github.com/muneeb-mbytes/SystemVerilog_Course/blob/b7_team_kachori/data_type/two_and_four_state/enum_data_type/set_value_enum/set_value_enum.sv

Github lab output link: https://github.com/muneeb-mbytes/SystemVerilog_Course/blob/b7_team_kachori/data_type/two_and_four_state/enum_data_type/set_value_enum/set_value_enum.log

enum method :

sl.no Method Description
1 first() returns the value of the first member of the enumeration
2 last() returns the value of the last member of the enumeration
3 next() returns the value of next member of the enumeration
4 prev() returns the value of previous member of the enumeration
5 num() returns the number of elements in the given enumeration
6 name() returns the string representation of the given enumeration value 
                                      Tabular column.5. enum methods

typedef enumerated data type

In typedef a type name can be given so that the same type can be used in many places.

Syntax : typedef enum enum_base_type(optional) {
<enum_name_declaration> = constant_expr(optional)...
} <enum_type_identifier>;

Example : typedef enum {MONDAY,
TUESDAY,
WEDNESDAY,
THURSDAY,
FRIDAY,
SATURDAY,
SUNDAY } week_e;
week_e = day;

In below figure declare typedef type and output using enum methods.

enum_typedef

                               Figure.19. Output of typedef enum using enum method

Github lab code link: https://github.com/muneeb-mbytes/SystemVerilog_Course/blob/b7_team_kachori/data_type/two_and_four_state/enum_data_type/typedef_enum/typedef_enum.sv

Github lab output link: https://github.com/muneeb-mbytes/SystemVerilog_Course/blob/b7_team_kachori/data_type/two_and_four_state/enum_data_type/typedef_enum/typedef_enum.log

String

A string type is a variable-length ordered collection of characters. The length of a string is the number of characters in the collection.

Syntax :string variable_name [= initial_value];

Example: string str = Manipal;

  • The memory space for strings is dynamically allocated.
  • The indices of string variables shall be numbered from 0 to N–1 (where N is the length of the string) so that index 0 is the first (leftmost) character of the string and index N–1 is the last (rightmost) character of the string.
  • An un-initialized or empty string is represented with the special value β€œβ€. An empty string has 0 length.

String operators cheat sheet

Operation Operator Description
Equality str1==str2 Returns 1 if the two strings are equal and 0 if they are not
Inequality str1!=str2 Returns 1 if the two strings are not equal and 0 if they are
Comparison str1 < str2, str1 <= str2, str1 > str2, str1 >= str2 Returns 1 if the corresponding condition is true and 0 if false
Concatenation {str1, str2, ..., strN} All strings will be concatenated into one resultant string
Replication {multiplier{str}} Replicates the string N number of times, where N is specified by the multiplier
Indexing str[index] Returns a byte, the ASCII code at the given index. If given index is out of range, it returns 0 
                                      Tabular column.6.string operators

Example:

Consider 2 strings, str1 as Manipal and str2 as Udupi,

  • Equality operator (str1 == str2), here the string 1 each letter ASCII value will be compared with string 2's of each letter sequentially, if it is equal then it will return 1 or else 0, here instead of 1 and 0 we're using statements. In this example, strings are not equal, because the ascii value of U is 85 and M is 77. Here the first letters ascii value are not same so it will display as strings are not equal.

  • Inequality operator (str1 != str2) , here the string 1 each letter ASCII value will be compared with string 2's of each letter sequentially, if it is not equal then it will return 1 or else 0, here instead of 1 and 0 we're using statements. In this example, strings are not equal, because the ascii value of U is 85 and M is 77. Here the first letters ascii value are not same so it will display as strings are not equal.

  • Comparison operator(>, => ,<, =<), here the string 1 each letter ASCII value will be compared with string 2's of each letter sequentially, here it will check for >, => ,<, =< condition, if any of these becomes true, it will return 1. Here as we discussed in the above points, U as large ascii value, so here string1 < string2 and string1 =< string2.

  • Concatenation operator ({str1,str2}), here 2 strings are concatenated and resultant is single string. So output will be ManipalUdupi.

Note: Using concatenation operator, we can concatenate the undeclared strings also, for example,
{str1,"Mangalore",str2}
Output - ManipalMangaloreUdupi

  • Replication operator ({2{str1}}), here it replicates the string N number of times, where N is specified by the multiplier. Here we're considering N as 2, so string1 will be replicated 2 times, and the output is ManipalManipal.

  • Displaying index letter (str1[i]), here we'll get the ascii character at mentioned index number. In this case, we've included for loop to display all the ascii characters of a string, so we get the output as
    M
    a
    n
    i
    p
    a
    l

The below figure.1 illustrates the output for string operators

string_oper2

                               Figure.20. Output of string operators

Github lab code link: https://github.com/muneeb-mbytes/SystemVerilog_Course/blob/b7_team_kachori/data_type/string/string_op/string_op.sv

Github lab output link: https://github.com/muneeb-mbytes/SystemVerilog_Course/blob/b7_team_kachori/data_type/string/string_op/string_op.log

String Methods cheat sheet

Function Description
str.len() Returns length of string.
str.putc() Used to assign one character of string.
str.getc() Returns a character.
str.tolower() Returns the lowercase of string.
str.toupper() Returns the uppercase of string.
str.compare(s) Returns the string compare result as ascii value.
str.icompare(s) Returns caseless string compare result as ascii value.
str.substr(i,j) Returns the sub string of main string. 
             Tabular column.7. string methods

Example:

Consider a string Manipal,

  • str.len(), here it will give the length of a string. As we considered Manipal, here there are 7 ascii character. So the output is 7.

  • str.putc(), it is used to assign one character of a string. So consider one temp variable to store the changes of the string and assign character "t" for 3rd index as given temp.putc(3, "t"). And the output we'll get as Mantpal.

  • str.getc(), it returns a character as output. Here mention the index of a character, which we want to get as output as given str.getc(1). And the output we get as a.

  • str.tolower(), it gives a string in lowercase. So the output will be manipal.

  • str.toupper(), it gives a string in uppercase. So the output will be MANIPAL.

  • str.compare(s), it will compare the string and gives output in ascii value. To make comparison, declare one more string as mirafra, and compare Manipal with mirafra. Here comparison will takes place with each character of a string Manipal with the each character of mirafra sequentially. Here ascii value of M = 77 and m = 109. So the difference between 77-109 is -32. So we get the output as -32.

  • str.icompare(s), it will compare the string without considering the cases of letters, and gives output in ascii value. As mentioned above, the strings are Manipal and mirafra, here it's a case insensitive comparison, M and m will consider as same, and next letters are a = 97 and i = 105, hence the difference between them is (97 - 105) -8. So the output is -8.

  • str.substr(i,j), it gives the sub string of main string. So we should mention the sub string indices which are to be displayed as given, str.substr(1,2). In Manipal the 1 and 2 index ascii characters are a and n. So the output will be an.

The below figure.2. shows the output of string methods.

string_method

                                      Figure.21. Output of string methods

Github lab code link: https://github.com/muneeb-mbytes/SystemVerilog_Course/blob/b7_team_kachori/data_type/string/string_me/string_method.sv

Github lab output link: https://github.com/muneeb-mbytes/SystemVerilog_Course/blob/b7_team_kachori/data_type/string/string_me/string_method.log