Issue Stage - vbnqwe/Poorly-made-Processor GitHub Wiki

Basic work in progress overview of issue stage: Once a destination register has been allocated in the rename stage, it will be sent to the issue stage on the next cycle. If a reservation station (RS) is available for the corresponding operation (RS will be separated into FP, integer, and mem categories), then the data for this instruction will be saved in the station. There will exist flags in each RS entry for each input register, once all the flags are high, that means that all the required data for the instruction is ready, meaning that the instruction in the RS can be sent into the execute stage.