OR1K Special Purpose Registers - v3l0c1r4pt0r/lkv-wiki GitHub Wiki
These are registers accessed via l.mfspr (read) and l.mtspr (write) instructions.
List by group
SYS (0)
| Id |
Name |
Brief |
| 0 |
VR |
Version register |
| 1 |
UPR |
Unit Present register |
| 2 |
CPUCFGR |
CPU Configuration register |
| 3 |
DMMUCFGR |
|
| 4 |
IMMUCFGR |
|
| 5 |
DCCFGR |
|
| 6 |
ICCFGR |
|
| 7 |
DCFGR |
|
| 8 |
PCCFGR |
|
| 16 |
NPC |
|
| 17 |
SR |
|
| 18 |
PPC |
|
| 32 |
EPCR0 |
|
| 47 |
EPCR15 |
|
| 48 |
EEAR0 |
|
| 63 |
EEAR15 |
|
| 64 |
ESR0 |
|
| 79 |
ESR15 |
|
DMMU (1)
| Id |
Name |
Brief |
| 0 |
DMMUCR |
Data MMU control register |
IMMU (2)
DC (3)
IC (4)
MAC (5)
D (6)
PC (7)
PM (8)
PIC (9)
TT (10)