Instruction Set Architecture - v3l0c1r4pt0r/lkv-wiki GitHub Wiki
Architecture described below is used at least on encoder processor. It is based on OpenRISC 1000 core (abbreviated or1k).
- single instruction is always 32-bits wide
- it is big endian
- it has 31 general purpose registers
- it can address offset of up to 65535 bytes around value in register
- slots similar to MIPS present, so on jump, instruction immediately after jump is executed simultaneously
Registers
There are 31 general purpose registers. r0 is fixed to zero, and causes a crash if any non-zero value is written to it.
r1 is typically used as a stack-pointer.
Encoding
R Type instruction
| Opcode | Destination | Source | Base | Offset |
|---|---|---|---|---|
| 6 bits | 5 bits | 5 bits | 5 bits | 11 bits |
I Type instruction
| Opcode | Destination | Source | Offset |
|---|---|---|---|
| 6 bits | 5 bits | 5 bits | 16 bits |
J Type instruction
| Opcode | Offset |
|---|---|
| 6 bits | 26 bits |
Jump address is computed by formula:
addr = offset * 4 + PC
where PC is program counter before execution of jump instruction
Instruction Set
Load Address (la)
$rt = $rs + 0x00
| Opcode | Param | Param | Offset |
|---|---|---|---|
0b101010 |
rt | rs | 0x00 |
Example
la $1,$2+0x1234
encodes to unpacked form:
0x2a 0x01 0x02 0x1234
and finally is packed into 32 bits:
0xa8221234
Instruction List
| Opcode | Name | Description | Type | Operation |
|---|---|---|---|---|
| 00 | jmpi | Jump | J | $pc += imm * 4 |
| 01 | call | Call | J | $r9 = $pc+4, $pc += imm * 4 |
| 02 | |
|||
| 03 | jnc | Jump if the comparison flag is clear | J | |
| 04 | jc | Jump if the comparison flag is set | J | |
| 05 | |
|||
| 06 | lh | Load high | I | $rt |= imm |
| 07 | - | Illegal instruction | - | - |
| 08 | I | |
||
| 09 | |
|||
| 0a | - | Illegal instruction | - | - |
| 0b | - | Illegal instruction | - | - |
| 0c | - | Illegal instruction | - | - |
| 0d | - | Illegal instruction | - | - |
| 0e | - | Illegal instruction | - | - |
| 0f | - | Illegal instruction | - | - |
| 10 | - | Illegal instruction | - | - |
| 11 | jmp | Jump to register address | R | $pc = $rb |
| 12 | |
|||
| 13 | |
|||
| 14 | - | Illegal instruction | - | - |
| 15 | - | Illegal instruction | - | - |
| 16 | - | Illegal instruction | - | - |
| 17 | - | Illegal instruction | - | - |
| 18 | - | Illegal instruction | - | - |
| 19 | - | Illegal instruction | - | - |
| 1a | - | Illegal instruction | - | - |
| 1b | - | Illegal instruction | - | - |
| 1c | - | Illegal instruction | - | - |
| 1d | - | Illegal instruction | - | - |
| 1e | - | Illegal instruction | - | - |
| 1f | - | Illegal instruction | - | - |
| 20 | - | Illegal instruction | - | - |
| 21 | lw | Load Word | R | $rt = *(u32*)($rs + $rb + imm) |
| 22 | - | Illegal instruction | - | - |
| 23 | lb | Load Byte | R | $rt = *(u8*)($rs + $rb + imm) |
| 24 | |
|||
| 25 | ls | Load Short Word | R | $rt = *(u16*)($rs + $rb + imm) |
| 26 | |
|||
| 27 | addi | Add immediate | I | $rt = $rs + signextend(imm) |
| 28 | addi | Add immediate | I | $rt = $rs + signextend(imm) |
| 29 | andi | Bitwise AND immediate | I | $rt = $rs & imm |
| 2a | ori | Bitwise OR immediate | I | $rt = $rs | imm |
| 2b | xori | Bitwise XOR immediate | I | $rt = $rs ^ signextend(imm) |
| 2c | multi | Signed multiply immediate | I | $rt = $rs * imm |
| 2d | Load from special register? | I | |
|
| 2e | shfti | Shift by immediate | I | If imm[7] is set: $rt = $rs ASR imm[5:0], otherwise if imm[6] is set: $rt = $rs >> imm[5:0], otherwise $rt = $rs << imm[5:0]. |
| 2f | cmpi | Compare register to immediate | I | Compare imm to $rs |
| 30 | R | |
||
| 31 | R/I | |
||
| 32 | - | Illegal instruction | - | - |
| 33 | - | Illegal instruction | - | - |
| 34 | - | Illegal instruction | - | - |
| 35 | sw | Store Word | R | *(u32*)($rt + $rb + imm) = $rs |
| 36 | sb | Store Byte | R | *(u8*)($rt + $rb + imm) = $rs |
| 37 | ss | Store Short Word | R | *(u16*)($rt + $rb + imm) = $rs |
| 38 | ext38 | Extended Instruction (see below) | R | ext_opcode=imm[3:0] |
| 39 | cmp | Compare Two Registers | R | Compare $rb to $rs |
| 3a | - | Illegal instruction | - | - |
| 3b | - | Illegal instruction | - | - |
| 3c | |
|||
| 3d | - | Illegal instruction | - | - |
| 3e | - | Illegal instruction | - | - |
| 3f | - | Illegal instruction | - | - |
ext38 Opcodes
| Opcode | Name | Description | Operation |
|---|---|---|---|
| 0 | add | Add | $rt = $rs + $rb |
| 1 | or | Bitwise OR | $rt = $rs | $rb |
| 2 | sub | Subtract | $rt = $rs - $rb |
| 3 | and | Bitwise AND | $rt = $rs & $rb |
| 4 | Bitwise OR | $rt = $rs | $rb |
|
| 5 | xor | Bitwise XOR | $rt = $rs ^ $rb |
| 6 | mul | Signed Multiply | $rt = $rs * $rb |
| 7 | mov | Copy Value | $rt = $rs |
| 8 | shl | Shift Left | $rt = $rs << $rb[5:0] |
| 9 | div | Divide | $rt = $rs / $rb |
| a | Divide | $rt = $rs / $rb |
|
| b | mov2 | Copy Value | $rt = $rb |
| c | movh | Copy High 16-bits | $rt = $rb << 16 |
| d | Bitwise AND | $rt = $rs & $rb |
|
| e | Copy Value | $rt = $rb |
|
| f | cmpf | Compare and Set Flags | ? |
0x306 is sometimes used for Signed Multiply. Does the 0x300 have some additional effect?
Comparison Instructions
The comparison performed by cmpi (0x2f) and cmp (0x39) instructions is controlled by the lower 3-bits value in the $rt field of the instruction i.e. bits [24:21].
$rt |
Comparison | Description |
|---|---|---|
| 0 | eq | $rs == imm or $rb |
| 1 | ne | $rs != imm or $rb |
| 2 | gt | $rs > imm or $rb |
| 3 | ge | $rs >= imm or $rb |
| 4 | lt | $rs < imm or $rb |
| 5 | le | $rs <= imm or $rb |
| 6 | z | false |
| 7 | - | false |