Clocks

The Barduino has one primary clock clock which is running at a frequency of 40 MHz. It also has 2 peripheral clocks for serial tilelink and jtag: tl_clock and jtag_TCK. clock and tl_clock have an uncertainty of 0.1 ns, while jtag_TCK has a 1 ns uncertainty.

Synthesis

Synthesis results are clean. The read_sdc commands all completed without any errors.

Place and Route

Here is the floorplan after place and route

Timing

Setup

Setup timing is clean, all paths are passing. It is also clean in the slow-slow corner.

Hold

There is one path violating hold timing with -42810 ps of negative slack. This is the only failing path in the fast-fast corner.

It appears to be a documented issue. Since it is a PoR path it can be safely disregarded

Power

From the power reports, the total power consumed by the design is 68.48 mW.

Power Type	Value (mW)	Percentage
Total Switching Power	36.23745129	52.9134%
Total Leakage Power	0.10487663	0.1531%
Total Power	68.48439376

Power by Category

Category	Internal Power (mW)	Switching Power (mW)	Leakage Power (mW)	Total Power (mW)	Percentage (%)
Sequential	14.46	3.707	0.05088	18.22	26.61%
Macro	9.919	4.52	0.02491	14.46	21.12%
IO	0	0	1.461e-09	≈0	≈0%
Physical-Only	0	0	2.93e-05	≈0	≈0%
Com

Power by Voltage Rail

Power Rail	Voltage (V)	Internal Power (mW)	Switching Power (mW)	Leakage Power (mW)	Total Power (mW)	Percentage (%)
VDDA	3.3	1.918	0.5604	0.0001059	2.479	3.62%
VDD	1.8	24.47	31.77	0.1045	56.35	82.28%
VDDIO	3.3	5.755	3.903	0.000259	9.658	14.1%

Clock Domain Power

Clock Name	Internal Power (mW)	Switching Power (mW)	Leakage Power (mW)	Total Power (mW)	Percentage (%)	Toggle Rate
tl_clock	0.09549	0.0873	2.943e-05	0.1828	0.267%	10 MHz
jtag_TCK	0.07801	0.08882	3.077e-05	0.1669	0.244%	8 MHz
clock	1.509	2.966	0.002372	4.478	6.54%	80 MHz
Total	1.683	3.142	0.002432	4.828	7.05%	—

The leakage hotspot for this design is the L2 Sram Block, it has a 22.9 μW leakage

Area