Resources from Hugo - tomdriley/cirkopt GitHub Wiki

On the linux servers, CMC provides documentation for the circuit characterization tool Liberate at:

/CMC/tools/cadence/LIBERATE18.10.293_lnx86/doc/liberate

Once we gain access to it, there will be a lot of good resources at Cadence Support. This includes Rapid Adoption Kits (RAKs) which have a lot of good examples and tutorials.

If we end up working on optimizing larger (multi-gate) circuits, this website has a lot of standard netlists that can be used for characterization (adders, ALUs, etc.). This stack exchange post has more information.

There are some open-source synthesis tools (translating Verilog to netlists), such as ABC, and yosys. I don't know we will use these but they could be useful.