Processes - tomas-fryza/vhdl-course GitHub Wiki

Combinational process is another way to describe combinational logic. A process is combinational if it does not infer any registers:

------------------------------------------------------------------------
-- p_label:
-- A description of the process and what it accomplishes goes here.
------------------------------------------------------------------------
p_label : process(<sensitivity list>)
begin
    <statements>
end process p_label;

Sensitivity list contains all signals that the process is sensitive to. If any of the signals change, the process will wake up, and the code within it is executed.

------------------------------------------------------------------------
-- p_alarm:
-- A combinational process of alarm clock.
------------------------------------------------------------------------
p_alarm : process(current_time, alarm_time)
begin
    if (alarm_time = current_time) then
        sound_alarm <= '1';
    else
        sound_alarm <= '0';
    end if;
end process p_alarm;

Sequential processes describes sequential logic. A process is sequential if it infers at least one register:

------------------------------------------------------------------------
-- p_sync_reset:
-- A sequential process with synchronous reset.
------------------------------------------------------------------------
p_sync_reset : process(clk)
begin
    if rising_edge(clk) then        -- Rising clock edge
        if (reset = '1') then
            <synchronous reset statements>
        else
            <normal operation statements>
        end if;
    end if;
end process p_sync_reset;
------------------------------------------------------------------------
-- p_sync_reset_enable:
-- A sequential process with synchronous reset and clock enable.
------------------------------------------------------------------------
p_sync_reset_enable : process(clk)
begin
    if rising_edge(clk) then        -- Rising clock edge
        if (reset = '1') then
            <synchronous reset statements>
        elsif (ce_i = '1') then
            <normal operation statements>
        end if;
    end if;
end process p_sync_reset_enable;

For a combinatorial process, all signals that are read should be included in the sensitivity list. For a clocked process, you need only the clock and reset signals in the sensitivity list.

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