Logic operators - tomas-fryza/vhdl-labs GitHub Wiki

Several logic operators are defined over the std_logic and std_logic_vector data type, such as not, and, or, nand, nor, xor, and xnor.

Concurrent assignment. Describes a wired connection:

c_o <= a_i and b_i;
d_o <= a_i or not(y_i);

Vector concatenation. To merge vectors, use & operator:

y_o <= '0' & x_i(3 downto 0);   -- y_o = "0 x_i3 x_i2 x_i1 x_i0"