How to create a new project in ISE - tomas-fryza/vhdl-course GitHub Wiki

Open Linux terminal from menu Start > Terminal Emulator or use shortcut Ctrl+Atl+T and run ISE application from terminal:
```
$ ise
```
Create a New project in menu File > New Project..., enter a name comparator (use letters, digits, and underscore only; first character can not be a digit), set location to your Documents folder (such as /home/lab661/Documents/your-name/Digital-electronics-1/Labs/02-ise), keep Top-level source type to HDL, use Next > button, and specify the following device and project properties.

Property Name Value

Product Category General Purpose

Family CoolRunner2 CPLDs

Device XC2C256

Package TQ144

Simulator ISim (VHDL/Verilog)

Preferred Language VHDL

Click on buttons Next > and Finish.
Create a new source file Project > New Source... > VHDL Module with file name top, click on Next >, do not specify any ports for module and click on Next > and Finish buttons. Replace the default top.vhd file by the following code.

Property Name	Value
Product Category	General Purpose
Family	CoolRunner2 CPLDs
Device	XC2C256
Package	TQ144
Simulator	ISim (VHDL/Verilog)
Preferred Language	VHDL

------------------------------------------------------------------------
--
-- VHDL template for combinational logic circuits.
-- Xilinx XC2C256-TQ144 CPLD, ISE Design Suite 14.7
--
-- Copyright (c) 2018-2020 Tomas Fryza
-- Dept. of Radio Electronics, Brno University of Technology, Czechia
-- This work is licensed under the terms of the MIT license.
--
------------------------------------------------------------------------

library ieee;
use ieee.std_logic_1164.all;

------------------------------------------------------------------------
-- Entity declaration for top level
------------------------------------------------------------------------
entity top is
port (
    BTN1, BTN0    : in  std_logic;
    LD2, LD1, LD0 : out std_logic
);
end entity top;

------------------------------------------------------------------------
-- Architecture declaration for top level
------------------------------------------------------------------------
architecture Behavioral of top is
begin
    LD2 <= '1';
    LD1 <= '0';
    LD0 <= BTN1 and BTN0;
end architecture Behavioral;

Save all files in menu File > Save All.