Entity - tomas-fryza/vhdl-course GitHub Wiki

The description of a module in a digital system can be divided into two views: the external view and the internal view. In VHDL, an entity declaration describes the external interface, including the number and types of inputs and outputs. The syntax rules for simplified description of entity declaration are:

entity identifier is
    port (
        port_name : mode data_type;
        other ports...
    );
end identifier;

The mode term can be in or out, which indicates that the corresponding signals flow "into" or "out" of the circuit. A simple example of an entity declaration is:

--------------------------------------------------
-- Entity declaration for adder
--------------------------------------------------
entity adder is
    port (
        a   : in  std_logic;
        b   : in  std_logic;
        sum : out std_logic
    );
end adder;

The example describes an entity titled adder, with two input ports and one output port, all of type std_logic. We can list the ports in any order. An input port allows us to model a device that senses data provided externally on a pin. An output port allows us to model a device that drives a pin to provide data to external connections.

The syntax rules for complex description of entity declaration are:

entity identifier is
    generic (
        generic_name : data_type := default_value;
        other generics...    
    );
    port (
        port_name : mode data_type;
        other ports...
    );
end identifier;

An example of more complex entity declaration is:

--------------------------------------------------
-- Entity declaration for top level
--------------------------------------------------
entity top_level is
    generic (
        g_LEDS : natural := 4
    );
    port (
        a    : in  std_logic;
        b    : in  std_logic;
        c    : out std_logic;
        dec  : out std_logic_vector(g_LEDS-1 downto 0)
    );
end top_level;

Generic allows us to pass information into an entity and component. Since a generic cannot be modified inside the architecture, it is like a constant.