Data types - tomas-fryza/vhdl-course GitHub Wiki

Two most common data types defined in the std_logic_1164 package are:

std_logic
std_logic_vector(<N - 1> downto 0)

The std_logic type represents an one-bit element and consists mainly of values '0' and '1'. (There are nine values in this type, but we are going to use only two of them.) The std_logic_vector data type is defined as an array of std_logic elements. Always define the range of an array in form N-1 downto 0, such as

a_i : in std_logic_vector(4 - 1 downto 0);

Note, you can also define your own type:

type t_my_states is (UP, RIGHT, DOWN, LEFT);
signal s_state: t_my_state;