Back to Main Project Page

OpenLane 2 Experience

I was able to synthesize my design using OpenLane at 15 ns. I tried to get down to 10 ns, but the OpenLane synthesis failed due to some timing violations when using the faster clock. The image below is what the 10 ns synthesis looked like. From this image, there were some things I noticed

The image below is what the 15 ns synthesis looked like.

From these images, there were some things I noticed with synthesis. I still had many setup violations in my synthesis, but OpenLane still was able to complete the flow and provide source files. This is what my design looks like using klayout:

The produced design is quite messy, as no hardening strategies, such as making macros, were used.

Congestion Issues with Iteration #1/#2

During my initial iterations of the HDL implementation, I was able to get it to a point where my simulation worked, so that I could start synthesizing. However, it would always stop at the routing stage of the OpenLane process. I took a look back at my code, and I found that I had a major oversight, being that I initiated the large memory arrays such as my k-value ROM, message schedule, and message buffer as simply large registers that do not have a clock. I had a suspicion that these were the cause of my OpenLane difficulties. As described in this section, I was able to fix many of my routing problems after implementing the clocked RAM modules.

Circular Errors for Iteration #4

Currently, the address from the compression loop and message controller is not registered. This kept throwing this warning in the Verilator linting log during synthesis.

After I fixed those issues as described in this section, I was able to maintain the 15 ns clock in my next synthesis via OpenLane.

Trying Out OpenRAM

OpenRAM was a tool that I found through researching solutions for my congestion problems, described in this section. I spent a good amount of time trying the tool out, but found some issues with it. For the things that were working, I was able to create a RAM macro using the provided configurations on their repository. However, I found these problems during my use of the tool:

• Documentation of the tool is very little, and only covers the bare minimum of starting a design.
• The tool's ROM feature is still in development, so I can not use it to replace my k-rom module.
• Custom configurations seem to fail, where only the provided configs work.

After looking around for some answers to my problems, I found that the repository is not being funded at the moment, so the tool has many issues. Thus, I decided not to go down this route and switched over to the solution described here.