iCE40 DSP Block - timvideos/litex-buildenv GitHub Wiki

Table 3. Instantiation Guide

Port Name	Input / Output	8x8 Multiplier	16x16 Multiplier	16x16 Accumulate	32x32 Accumulate	16x16 Adder/Subtractor	32x32 Adder/Subtractor	8x8 MAC	16x16 MAC
ACCUMCI	Input	Default	Default	Bottom	Signal	Default -> Bottom	Default -> Signal	Default -> Bottom	Default -> Signal
ADDSUBTOP	Input	Default	Default	0	0	0=Add, 1=Sub	0=Add, 1=Sub	0	0
AHOLD	Input	Signal	Signal	Top -> Signal	Signal	Top -> Signal	Signal	Signal	Signal
A[15:8]	Input	Top	Signal	Top	Signal	Top	Signal	Top	Signal
A[7:0]	Input	Bottom	Signal	Top	Signal	Top	Signal	Bottom	Signal
BHOLD	Input	Signal	Signal	Bottom -> Signal	Signal	Bottom -> Signal	Signal	Signal	Signal
B[15:8]	Input	Top	Signal	Bottom	Signal	Bottom	Signal	Top	Signal
B[7:0]	Input	Bottom	Signal	Bottom	Signal	Bottom	Signal	Bottom	Signal
CE	Input	Signal	Signal	Signal	Signal	Signal	Signal	Signal	Signal
CHOLD	Input	Default	Default	Default -> Top	Default -> Signal	Top	Default -> Signal	Top	Signal
CI	Input	Default	Default	Default	Default	Bottom	Signal	Default	Default
CLK	Input	Signal	Signal	Signal	Signal	Signal	Signal	Signal	Signal
C[15:0]	Input	Default	Default	Default -> Top	Default -> Signal	Top	Default -> Signal	Top	Signal
DHOLD	Input	Default	Default	Default -> Bottom	Default -> Signal	Bottom	Default -> Signal	Bottom	Signal
D[15:0]	Input	Default	Default	Default -> Bottom	Default -> Signal	Bottom	Default -> Signal	Bottom	Signal
IRSTBOT	Input	Bottom -> Signal	Signal	Bottom -> Signal	Signal	Bottom -> Signal	Signal	Bottom -> Signal	Signal
IRSTTOP	Input	Top -> Signal	Signal	Top -> Signal	Signal	Top -> Signal	Signal	Top -> Signal	Signal
OHOLDBOT	Input	Bottom -> Default	Signal -> Default	Bottom	Signal	Bottom	Signal	Bottom	Signal
OHOLDTOP	Input	Top -> Default	Signal -> Default	Top	Signal	Top	Signal	Top	Signal
OLOADBOT	Input	Default	Default	Signal	Signal	0	0	Signal	Signal
OLOADTOP	Input	Default	Default	Signal	Signal	0	0	Signal	Signal
ORSTBOT	Input	Bottom	Signal	Bottom	Signal	Bottom	Signal	Bottom	Signal
ORSTTOP	Input	Top	Signal	Top	Signal	Top	Signal	Top	Signal
SIGNEXTIN	Input	Default	Default	Bottom	Signal	Bottom	Signal	Default -> Bottom	Default -> Signal
ACCUMCO	Output	Default	Default	Top	Signal	Default -> Top	Default -> Signal	Default -> Top	Default -> Signal
CO	Output	Default	Default	Default -> Top	Default -> Signal	Top	Signal	Default -> Top	Default -> Signal
OUTPUT[15:0]	Output	Bottom	Signal	Bottom	Signal	Bottom	Signal	Bottom	Signal
OUTPUT[31:16]	Output	Top	Signal	Top	Signal	Top	Signal	Top	Signal
SIGNEXTOUT	Output	Default	Default	Top	Signal	Top	Signal	Default -> Top	Default -> Signal
ADDSUBBOT	Input	?????????????????	????????????????	??????????????????	??????????????????	??????????????????????	??????????????????????	?????????????????	?????????????????
	0=Add, 1=Sub	0=Add, 1=Sub	0	0	0=Add, 1=Sub	0=Add, 1= Sub	0=Add, 1=Sub	0	0

Compare too;

DSP: Preliminary Mapping  Report (see note below)
+------------+------------------+--------+--------+--------+--------+--------+------+------+------+------+-------+------+------+                                                                                                             
|Module Name | DSP Mapping      | A Size | B Size | C Size | D Size | P Size | AREG | BREG | CREG | DREG | ADREG | MREG | PREG |                          
+------------+------------------+--------+--------+--------+--------+--------+------+------+------+------+-------+------+------+                                                                                                             
|lm32_cpu    | A2*B2            | 18     | 16     | -      | -      | 48     | 1    | 1    | -    | -    | -     | 0    | 0    |                          
|lm32_cpu    | (PCIN>>17)+A2*B2 | 16     | 16     | -      | -      | 48     | 1    | 1    | -    | -    | -     | 0    | 1    |                                                                                                             
|lm32_cpu    | A2*B2            | 18     | 18     | -      | -      | 48     | 1    | 1    | -    | -    | -     | 0    | 0    |                          
|lm32_cpu    | (PCIN>>17)+A2*B2 | 18     | 16     | -      | -      | 48     | 1    | 1    | -    | -    | -     | 0    | 1    |                                                                                                             
+------------+------------------+--------+--------+--------+--------+--------+------+------+------+------+-------+------+------+   


|5     |DSP48E1    |     2|
|6     |DSP48E1_1  |     1|