We are currently using ixo-usb-jtag and OpenOCD.

Old stuff

xc3sprog

xc3sprog is a suite of utilities for programming Xilinx FPGAs, CPLDs, and EEPROMs with the Xilinx Parallel Cable and other JTAG adapters under Linux.

jtaghs1	USB	Digilent JTAG-HS1 cable
jtaghs2	USB	Digilent JTAG-HS2 cable
xpc	USB	Xilinx Platform Cable USB II (DLC10), or on-board programmer (e.g. Spartan 3E starter kit)

http://sourceforge.net/mailarchive/forum.php?thread_name=20121203203522.7b0c0f7e%40bever&forum_name=xc3sprog-users
I just got an Atlys board. I can confirm that xc3sprog programs the
Spartan-6 FPGA on the Atlys board without any issues if a separate JTAG
cable is used.

The Atlys board also has an on-board JTAG-USB programmer based on a
Cypress FX2, but it uses a proprietary USB protocol and therefore does
not work with xc3sprog.

Programming the SPI flash chip on the Atlys board needed some work.
xc3sprog SVN r717 gives the following error message:
  Found Numonyx Device, Device ID 0xba18
  M25P: Unexpected RDID upper Device ID 0xba

I added support for N25Q devices in progalgspiflash.cpp to fix it.
This is now committed in SVN r718 (shout if you disagree).

Of course, a bscan_spi bitfile is needed to access the SPI memory. The
xc3sprog distribution already contains xc6slx45-fg484.bit which appears
to work with the Atlys board. However, the Atlys FPGA is xc6slx45-csg324.
Do you know if it is safe to use bscan_spi files for a different
package, or should I build a separate bitfile for csg324?

Kind regards, Joris.

ixo.de USB JTAG pod

http://ixo-jtag.sourceforge.net/

nexys2prog - Easy programming of Digilent's Nexys(2)

This Perl script greatly simplifies the programming of a Digilent Nexys/Nexys2 board under Linux. It is well documented, see the links below.

http://ixo-jtag.svn.sourceforge.net/viewvc/ixo-jtag/nexys2prog/trunk/README.txt?view=markup
44	The Digilent Nexys 2 is a great FPGA development board, with a ton of
45	I/O available on board, a very large (XC3S1200E) FPGA part available,
46	and an excellent selection of add-on devices for a very reasonable
47	price.
48	
49	It is also, like most such devices, completely unsupported under
50	linux.  Nonetheless it can be made to work, via a distressingly long
51	chain of responsibility.  Bear with me, I think I have most of this
52	puzzled out:
53	
54	Xilinx, of course, provides a Linux version of their free (as-in-beer)
55	ISE WebPack product [1].  But Digilent uses a proprietary protocol for
56	their USB interface, and they neither document it nor provide tools
57	other than a (decidedly clunky) Windows GUI [2] to use it.
58	
59	Nonetheless the USB hardware on the device is open.  The Cypress FX2
60	USB chip on the board, which itself is a 8051 microcontroller, is
61	fully programmable from across the USB bus [3] and that interface is
62	supported from linux thanks to the work of the linux-hotplug project
63	[4].  The sdcc project provides a free C compiler [5] for the 8051,
64	which Kolja Waschk used to write a firmware suite named "usb_jtag" [6]
65	for a FX2-based USB/JTAG cable that allows it to be used as a
66	compatible replacement for an Altera USB Blaster -- a cable based on a
67	different USB interface part from FTDI, which is supported under linux
68	by the libftdi project [7].  The UrJTAG project [8], which is a
69	currently-maintained fork of the mostly-abandonware openwince-jtag
70	project, provides a high level JTAG interface (using libftdi as one of
71	many drivers) that can be used to program the FPGA using SVF files
72	from the Xilinx iMPACT tool.  The Nexys 2 board enters the picture at
73	last when Sune Mai, in posts on fpga4fun.com [9] and on the UrJTAG
74	mailing list [10], ported Waschk's usb_jtag firmware to the Nexys 2 by
75	simply changing the 8051 port assignments of the JTAG pins (the FX2 on
76	the Digilent board is wired differently than the usb_jtag cable, but
77	is otherwise compatible) and by fixing a integer overflow bug the
78	upstream code had with handling large bitstream files.  Neither change
79	has been merged into Kolja's code, unfortunately.
80	
81	Finally, Morgan Delahaye-Prat collected the above into a single
82	walkthrough on his (French) blog [11], providing detailed instructions
83	and downloadable files and patches.  The language barrier for
84	non-French-speakers can be surmounted without too much difficulty via
85	google's language tools.  The Rube Goldberg-like complexity of the
86	process, however, took much longer to puzzle out and left me with a
87	tree full of tiny scripts, notes, and patched software trees.
88	
89	So at last we come to my contribution.  This nexys2prog script tries
90	to eliminate as much complexity as possible.  The script will
91	automatically probe the USB bus to detect the Nexys 2 board and
92	reconfigure it if necessary using a pre-built firmware image stored in
93	the script itself.  It will automatically generate SVF files from
94	Xilinx bitstream images, and push them to the device using a
95	configuration automatically generated from data files in the ISE tree
96	and a built-in notion of how the JTAG bus on the board is configured.
97	The user, ultimately, is responsible only for invoking the script with
98	the name of a .bit file they would like to push to the FPGA.
99	
100	External dependencies have been limited to just Xilinx ISE (required
101	for anyone doing development), fxload (available via apt-get from
102	Debian or Ubuntu), libftdi1 (likewise a Debian package), and UrJTAG
103	(source package buildable with a simple "configure;make;make
104	install").  A permissions issue with USB device files on Ubuntu
105	requires a small modification to the udev configuration, or simply
106	running the script as root.

FX2

The main goal of the FX2 chip is to provide an efficient replacement to the USB-Blaster cable from Altera. This cable allows connecting an USB port from a PC to the the JTAG port of a FPGA. http://fpga4u.epfl.ch/wiki/FX2

NeroJTAG

http://www.makestuff.eu/wordpress/software/nerojtag/ NeroJTAG is a simple USB JTAG adaptor. The idea is to define an open JTAG-over-USB protocol that can be implemented by several different hardware platforms.

FX2LP Implementation

The Cypress FX2LP implementation is based on Dennis Muhlestein's fx2lib. It was designed to be hardware-compatible with the Digilent Nexys2. The FX2LP's support for HiSpeed USB makes it a good choice for communicating with FPGA designs, so the FX2LP implementation of NeroJTAG is part of a larger project, FPGALink. If you have a standalone FX2LP, you need to connect it like this (again, if you're paranoid, connect via 100Ω resistors):

Pinout

Port D on the Cypress FX2 is connected to the XC6LX45 (the FPGA)'s JTAG port:

| FX2 | FPGA JTAG |
| PD0 | TDO |
| PD2 | TDI |
| PD3 | TMS |
| PD4 | TCK |

(It is not confirmed that these are the only pins required for programming)