HowTo Yosys Vivado FPGA Flow - timvideos/litex-buildenv GitHub Wiki

Instructions to use Yosys + Vivado flow and boot Linux on Arty board

This is a modified version of the HowTo LCA2018 FPGA Miniconf VexRiscv Renode.

Download & Install Vivado

The Xilinx Vivado toolchain is 16GB and may take many hours to download.

Follow the instructions on the LiteX BuildEnv Wiki to download, install and get a license to Vivado.

Download & Install LiteX Dependencies

Install bash, wget and realpath (part of coreutils in newer Ubuntu / Debian).

Download & setup udev rules

git clone https://github.com/litex-hub/litex-buildenv-udev
cd litex-buildenv-udev
make install

Reload udev rules:

sudo udevadm control --reload-rules

Get the right permissions

sudo adduser $USER video
sudo adduser $USER dialout
sudo reboot

Download & setup the LiteX Build Environment

git clone https://github.com/timvideos/litex-buildenv.git
cd litex-buildenv
export CPU=vexriscv PLATFORM=arty TARGET=net
./scripts/download-env.sh
source ./scripts/enter-env.sh
(LX P=arty C=vexriscv) $

You should have "(LX P=arty C=vexriscv)" in your bash prompt now.

Resuming Development

So you walked away and now need to start a new session. Here's how:

cd litex-buildenv
export CPU=vexriscv PLATFORM=arty TARGET=net
source ./scripts/enter-env.sh
(LX P=arty C=vexriscv) $

Test building gateware

This tests that you have Yosys and Vivado successfully installed and are able to build gateware for the FPGA within a reasonable amount of time.

Enter the LiteX Build Environment and then type:

(LX P=arty C=vexriscv) $ MAKE_LITEX_EXTRA_CMDLINE="--build-option synth_mode yosys" make gateware
...
Writing log file ./top.prm
===================================
Configuration Memory information
===================================
File Format        BIN
Interface          SPIX4
Size               16M
Start Address      0x00000000
End Address        0x00FFFFFF

Addr1         Addr2         Date                    File(s)
0x00000000    0x0021728B    Jan 15 18:52:20 2020    top.bit
0 Infos, 0 Warnings, 0 Critical Warnings and 0 Errors encountered.
write_cfgmem completed successfully
# quit
INFO: [Common 17-206] Exiting Vivado at Wed Jan 15 18:52:25 2020...

real    3m52.418s
user    5m16.642s
sys     0m19.159s
(LX P=arty C=vexriscv) $

Load bitstream on FPGA now :

(LX P=arty C=vexriscv) make gateware-load
openocd -f board/digilent_arty.cfg -c "init; pld load 0 build/arty_net_vexriscv//gateware/top.bit; exit"
Open On-Chip Debugger 0.10.0+dev-01012-ged8fa09cf-dirty (2020-01-15-04:14)
Licensed under GNU GPL v2
For bug reports, read
        http://openocd.org/doc/doxygen/bugs.html
Info : auto-selecting first available session transport "jtag". To override use 'transport select <transport>'.
jtagspi_program
Info : ftdi: if you experience problems at higher adapter clocks, try the command "ftdi_tdo_sample_edge falling"
Info : clock speed 10000 kHz
Info : JTAG tap: xc7.tap tap/device found: 0x0362d093 (mfg: 0x049 (Xilinx), part: 0x362d, ver: 0x0)

Now we need to upload a firmware. Since board already booted, press enter and type "serialboot" command in order to start loading:

(LX P=arty C=vexriscv) [micko@beast litex-buildenv]$ make firmware-load

...
chmod -x firmware.bin
python -m litex.soc.software.mkmscimg -f --little firmware.bin -o firmware.fbi
make[1]: Leaving directory '/home/micko/src/litex-buildenv/build/arty_net_vexriscv/software/firmware'

real    0m4.451s
user    0m3.852s
sys     0m0.406s
flterm --port=/dev/ttyUSB1 --kernel=build/arty_net_vexriscv//software/firmware/firmware.bin --speed=115200
[FLTERM] v2.4-29-g47d3b15 Starting...

litex> serialboot
Booting from serial...
Press Q or ESC to abort boot completely.
sL5DdSMmkekro
[FLTERM] Received firmware download request from the device.
[FLTERM] Uploading kernel (57152 bytes)...
[FLTERM] Upload complete (7.7KB/s).
[FLTERM] Booting the device.
[FLTERM] Done.
Executing booted program at 0x40000000

--============= Liftoff! ===============--
HDMI2USB firmware booting...


hardware version info
===============================================
           DNA: 00541d2e50210854
           MAC: Unknown

gateware version info
===============================================
      platform: arty
        target: net
      revision: be809038ea75a313e8b6bb236c7643a51c1526fb

firmware version info
===============================================
      platform: arty
        target: net
    git commit: be809038ea75a313e8b6bb236c7643a51c1526fb
    git branch: master
  git describe: v0.0.4-681-gbe80903-dirty
    git status:
    --
     M ../../../../scripts/settings.sh
     m ../../../../third_party/litex
    --

         built: Jan 15 2020 18:54:46
        uptime: 00:00:00
-----------------------------------------------
MDIO mode: Reserved / link: up
uIP init done with ip 192.168.100.50
Etherbone listening on port 1234
Telnet listening on port 23
H2U 00:00:00>

Linux

Dependencies

Make sure you have TFTP installed and setup as described at this link.

If you have wired network feel free to use additional IP on same Ethernet device, like (where eno1 is our main network device):

ip addr add 192.168.100.100/24 dev eno1 label eno1:0

Building Linux Kernel

Please note that next will take a while. It downloads kernel sources and compiles.

$ export CPU=vexriscv CPU_VARIANT=linux PLATFORM=arty TARGET=net FIRMWARE=linux
$ source ./scripts/enter-env.sh
(LX P=arty C=vexriscv.linux F=linux) $
(LX P=arty C=vexriscv.linux F=linux) $ ./scripts/build-linux.sh

Building gateware

If you have exited the LiteX environment, you will need to re-enter it. See "Resuming Development" above.

$ export CPU=vexriscv CPU_VARIANT=linux PLATFORM=arty TARGET=net FIRMWARE=linux
$ source ./scripts/enter-env.sh
(LX P=arty C=vexriscv.linux F=linux) $ 

And build gateware same as in first test flow :

(LX P=arty C=vexriscv.linux F=linux) $ MAKE_LITEX_EXTRA_CMDLINE="--build-option synth_mode yosys" make gateware

Booting Linux

If you need to manually stop or start the tftp server (e.g. after a reboot), then you can use

(LX P=arty C=vexriscv.linux F=linux) $ make tftpd_stop          # Stop any previously run tftp server

After that :

(LX P=arty C=vexriscv.linux F=linux) $ make tftpd_start         # Start the tftp server again
(LX P=arty C=vexriscv.linux F=linux) $ make tftp                # Copy firmware to tftp server directory
(LX P=arty C=vexriscv.linux F=linux) $ make gateware-load       # Load gateware
(LX P=arty C=vexriscv.linux F=linux) $ make firmware-connect    # Connect to the serial console

And it boots :

...
Downloaded 1842 bytes from rv32.dtb over TFTP to 0xc1000000
Downloaded 2992 bytes from emulator.bin over TFTP to 0x50000000
Executing booted program at 0x50000000

--============= Liftoff! ===============--
*** VexRiscv BIOS ***
*** Supervisor ***
No DTB passed to the kernel
Linux version 5.0.0 (micko@) (gcc version 9.1.0 (9.1.0)) #1 Wed Jan 15 17:03:18 CET 2020
Initial ramdisk at: 0x(ptrval) (8388608 bytes)
Zone ranges:
  Normal   [mem 0x00000000c0000000-0x00000000c1ffffff]
Movable zone start for each node
Early memory node ranges
  node   0: [mem 0x00000000c0000000-0x00000000c1ffffff]
Initmem setup node 0 [mem 0x00000000c0000000-0x00000000c1ffffff]
elf_hwcap is 0x1101
Built 1 zonelists, mobility grouping on.  Total pages: 8128
Kernel command line: mem=32M@0x40000000 rootwait console=hvc0 root=/dev/ram0 init=/sbin/init swiotlb=32
Dentry cache hash table entries: 4096 (order: 2, 16384 bytes)
Inode-cache hash table entries: 2048 (order: 1, 8192 bytes)
Sorting __ex_table...
Memory: 21596K/32768K available (1950K kernel code, 90K rwdata, 318K rodata, 104K init, 184K bss, 11172K reserved, 0K cma-reserved)
SLUB: HWalign=64, Order=0-3, MinObjects=0, CPUs=1, Nodes=1
NR_IRQS: 0, nr_irqs: 0, preallocated irqs: 0
clocksource: riscv_clocksource: mask: 0xffffffff max_cycles: 0xffffffff, max_idle_ns: 25483472618 ns
sched_clock: 32 bits at 75MHz, resolution 13ns, wraps every 28633115129ns
Console: colour dummy device 80x25
printk: console [hvc0] enabled
Calibrating delay loop (skipped), value calculated using timer frequency.. 150.00 BogoMIPS (lpj=300000)
pid_max: default: 32768 minimum: 301
Mount-cache hash table entries: 1024 (order: 0, 4096 bytes)
Mountpoint-cache hash table entries: 1024 (order: 0, 4096 bytes)
devtmpfs: initialized
clocksource: jiffies: mask: 0xffffffff max_cycles: 0xffffffff, max_idle_ns: 7645041785100000 ns
futex hash table entries: 256 (order: -1, 3072 bytes)
clocksource: Switched to clocksource riscv_clocksource
Unpacking initramfs...
Initramfs unpacking failed: junk in compressed archive
workingset: timestamp_bits=30 max_order=13 bucket_order=0
Block layer SCSI generic (bsg) driver version 0.4 loaded (major 254)
io scheduler mq-deadline registered
io scheduler kyber registered
random: get_random_bytes called from init_oops_id+0x4c/0x60 with crng_init=0
Freeing unused kernel memory: 104K
This architecture does not have kernel memory protection.
Run /init as init process
mount: mounting tmpfs on /dev/shm failed: Invalid argument
mount: mounting tmpfs on /tmp failed: Invalid argument
mount: mounting tmpfs on /run failed: Invalid argument
Starting syslogd: OK
Starting klogd: OK
Initializing random number generator... random: dd: uninitialized urandom read (512 bytes read)
done.
Starting network: ip: socket: Function not implemented
ip: socket: Function not implemented
FAIL

Welcome to Buildroot
buildroot login: 

You can now login as root (no password needed):

buildroot login: root
login[48]: root login on 'hvc0'
# uname -a
Linux buildroot 5.0.0 #1 Wed Jan 15 17:03:18 CET 2020 riscv32 GNU/Linux
# 
# 
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