InstructionGrain Methodology and System Layering Overview - timothyPeer/VirtualASA GitHub Wiki

πŸ“„ InstructionGrain Methodology

We designed the emulator to use a singleton InstructionGrain wrapper for each instruction. This encapsulates all processing and logic for a single architectural instruction, based on the Alpha System Architecture (ASA) specification.

Key Points:

Each InstructionGrain is instantiated once and lives for the lifetime of the emulator, reducing memory churn and improving dispatch efficiency.

Around 700 grains have been implemented, each consuming ~1–3 KB of memory.

Grains are generated using a common factory, and they are released for testing and use in controlled batches.

Instructions that are illegal, unsupported, or decoded outside the ASA specification are handled by the dedicated IllegalInstructionGrain object, which raises appropriate exceptions and logs diagnostic information.

This architecture ensures that decoding, execution, profiling, and exception handling for each instruction are cleanly separated and encapsulated.

πŸ“„ System Layering Introduction

The emulator is architected in clearly defined layers to support maintainability, testing, and correctness:

πŸ”· Registers

The RegisterBank layer provides access to both integer and floating-point registers, along with helper methods for single/double precision access. It integrates with FPCR for floating-point control and status.

πŸ”·** AlphaCPU**

The AlphaCPU is the execution core. It orchestrates the instruction cycle, interacts with memory, TLB, registers, and manages exceptions and traps. It also integrates profiling and execution state.

πŸ”· AlphaSystemMemory

This layer handles RAM and ROM with protection and translation support. It is responsible for physical and virtual memory operations.

  • πŸ”· TLB (Translation Lookaside Buffer)

The TLB provides virtual-to-physical address translation with caching of page table entries, supporting both instruction and data fetches.

πŸ”· Caching

Above the TLB, the emulator provides instruction and data caches, emulating the Alpha’s multi-level cache hierarchy, and integrating coherency mechanisms.

These layers interact cleanly, with the CPU at the center orchestrating interactions with memory and registers, mediated by TLB and caches where appropriate.