The iCE40 FPGA

The iCE40 from Lattice Semiconductor is not the most powerful, but features a fully open source design flow. Details can be found here. Lattice also provides a free license for this series of product. Key features for the implementation of VGA include the ability to generate PLLs on board, as well as hard IP SPI blocks (not used, but valuable for future MBED integration).

Implementation was short and sweet. A 25.13MHz PLL was generated using the PLL wizard from Lattice. Key frame constants were created (think of these as match registers) that were compared to horizontal and vertical counters. These counters incremented on the PLL, so each increment corresponds to a pixel.

HSYNC and VSYNC simply triggered on a match between the frame constants and the location counters. Timing was verified using the Agilent 54622D: