Demo

While studied heavily, issues with linked list control limited the implementation of a fully featured DMA->I2S pixel line. On-the-fly clock reconfiguration for the VSYNC signal also proved troublesome.

Despite this, software was created that does create a valid VGA signal recognized by monitors. While poor practice, wait commands were used as a temporary solution to create the VSYNC signal. The pixel line was simply held high.

Above is an example of the monitor recognizing the VGA signal from the MBED. Due to slight timing inaccuracies (due to high error in wait), the monitor assumes a custom resolution.

An older CRT monitor was tested that does not require blanking on the pixel line. It recognized the high pixel line. In the experiment this was tied to the 'blue' pixel line, resulting in a solid blue image.