LPC1768 Hardware

Referring back to the VGA page, in order to create a VGA signal, a device must be capable of the following:

• Output an arbitrary bitstream at ~25MHz (pixel line)
• Generate a high frequency, time accurate, out-of-phase periodic pulse (horizontal sync)
• Generate a low frequency, time accurate, out-of-phase periodic pulse (vertical sync)

The ARM Cortex-M3 microprocessor within the LPC1768 microcontroller is not capable of such a feat. In fact, such time accurate parallel processes are not really suited for this kind of device. Fortunately, the LPC1768 features many rich peripherals that can be exploited to carry out the tasks listed above.

With 32k of internal RAM, an entire 640x480 frame can be stored. The direct memory access (DMA) controller can effectively pipe this data at fast enough speeds to support the 25MHz pixel data. I2S, a serial bus standard designed for connecting audio devices together, features an 8 word FIFO data buffer for its transmit line. This allows for a continuous bitstream to a physical pin of the device, substantiating the pixel data line. I2S is the only peripheral that can support such a continuous stream. SSP was explored but found to generate a ~1 clock delay in-between words; which would result in desync with the monitor and visible vertical black lines. The PWM peripheral supports double ended pulse triggers, which is effectively phase control. This allows for accurate generation of the horizontal sync pulse. Unfortunately, there is only one PWM timer. This prevents VSYNC from also being implemented on a separate PWM channel. The general purpose timers do not support double ended trigger like the PWM timer does, but by toggling on trigger and then re-configuring the timer - a VSYNC signal can be generated. This can only be afforded due to the relatively slow nature of VSYNC.

By offloading all of the tasks above onto the peripherals of the device, the microprocessor can operate freely to handle complex operations such as font handling and active manipulation of the frame buffer.