Voltage rail calculations - t-shaw374/209_group7_2026 GitHub Wiki
VOLTAGE RAIL CALCULATIONS
-Thomas Shaw
Overview
Purpose: Step the 7 V buck output down to a 5 V power rail and a 3.3 V reference rail using LM1117 fixed-output LDO regulators, and generate a buffered 1.65 V offset (Vref) for the signal conditioning.
- Input: 7 V from the LM2596 buck stage (6.80–7.22 V across the LM2596 reference tolerance)
- Outputs:
- 5 V power rail (V1): powers the MCU, op-amps, display and ESP32
- 3.3 V reference rail (V2): used for the ADC reference (AREF) and the offset divider only
- 1.65 V Vref (U8B): centres both signal conditioning outputs in the ADC range
| Ref |
Part |
Value / Role |
| V1 |
LM1117-5.0 |
5 V power rail |
| V2 |
LM1117-3.3 |
3.3 V reference rail |
| C19 |
Electrolytic |
47 µF, 5 V regulator input |
| C20 |
Electrolytic |
47 µF, 5 V regulator output |
| C34 |
Electrolytic |
47 µF, 3.3 V regulator input |
| C35 |
Electrolytic |
47 µF, 3.3 V regulator output |
| R25, R26 |
Resistors |
10 kΩ each, Vref divider |
| C15 |
Ceramic |
100 nF, 3.3 V rail bypass at divider |
| C17 |
Ceramic |
100 nF, divider filter |
| U8B |
TLC082 |
Unity-gain voltage follower |
| C33 |
— |
Not fitted |
Why two separate regulators
- The 5 V rail sees large, fast load steps: ESP32 BLE bursts (~300 mA) and display updates
- If the ADC reference shared that rail, every load step would shift AREF and appear as a measurement error
- The 3.3 V rail only supplies AREF and the offset divider, so its load is tiny and constant
- A constant load means the LM1117's load regulation has almost nothing to correct, so the reference stays stable
- Both AREF and the 1.65 V offset come from the same 3.3 V rail, so the offset is ratiometric: if the 3.3 V rail drifts, the offset still lands at mid-scale ADC code
Rail loads
| Rail |
Load |
Current |
| 5 V |
MCU, op-amps, display, ESP32 |
72 mA typical, 366 mA peak |
| 3.3 V |
Vref divider (3.3 V / 20 kΩ) |
0.165 mA |
| 3.3 V |
AREF pin (~32 kΩ input resistance) |
~0.1 mA |
| 3.3 V |
Total |
~0.27 mA |
LM1117 Regulators
Key datasheet values (LM1117, 0 to 125 °C)
| Parameter |
Value |
| Max output current |
800 mA |
| Input voltage |
15 V recommended max, 20 V abs max |
| Dropout (100 mA / 500 mA / 800 mA) |
1.1 / 1.15 / 1.2 V typ, 1.2 / 1.25 / 1.3 V max |
| Quiescent current |
5 mA typ, 10 mA max |
| Current limit |
800 mA min, 1.2 A typ |
| Ripple rejection |
75 dB typ, 60 dB min (120 Hz) |
| RθJA (SOT-223) |
61.6 °C/W |
| Junction temperature design limit |
125 °C |
Output voltage accuracy
| Rail |
At 25 °C (10 mA) |
Full range (0–800 mA, full temp) |
| 5 V |
4.95–5.05 V (±1%) |
4.90–5.10 V (±2%) |
| 3.3 V |
3.267–3.333 V (±1%) |
3.235–3.365 V (±2%) |
- A 3.3 V error scales every ADC reading by the same percentage, so it appears as a gain error of up to ±1% at room temperature
- This is within the ±5% measurement spec, and can be calibrated out in firmware
Dropout headroom
The LM1117 needs V_IN ≥ V_OUT + dropout to regulate:
5 V rail: V_IN − V_OUT = 7.01 − 5.0 = 2.01 V (worst case 6.80 − 5.0 = 1.80 V)
3.3 V rail: V_IN − V_OUT = 7.01 − 3.3 = 3.71 V (worst case 3.50 V)
| Rail |
Load |
Max dropout |
Worst-case headroom |
OK |
| 5 V |
366 mA (peak) |
~1.25 V |
1.80 V |
✅ (0.55 V margin) |
| 3.3 V |
~0.27 mA |
1.2 V |
3.50 V |
✅ |
- The 7 V buck output was chosen to give the 5 V regulator enough headroom over its ~1.25 V dropout, without dissipating more power than necessary
Power dissipation and temperature
P = (V_IN − V_OUT) × I_LOAD + V_IN × I_Q (I_Q ≈ 5 mA)
ΔT_J = P × RθJA (SOT-223: 61.6 °C/W)
| Rail |
Load |
V_IN |
P |
ΔT_J |
| 5 V |
72 mA (typical) |
7.01 V |
0.18 W |
11 °C |
| 5 V |
366 mA (peak) |
7.01 V |
0.77 W |
48 °C |
| 5 V |
366 mA (peak) |
7.22 V |
0.85 W |
52 °C |
| 3.3 V |
~0.27 mA |
7.01 V |
0.036 W |
2 °C |
- Even at sustained peak load, T_J ≈ 25 + 52 = 77 °C, well below the 125 °C design limit
- Peak load is a short burst, so the real temperature rise is much lower
- The 3.3 V regulator's dissipation is almost entirely its own quiescent current
- The tab (pin 4) is V_OUT. A copper pour on the tab pad acts as the heatsink
Capacitors (C19, C20, C34, C35 = 47 µF)
Datasheet requirements
- Input: 10 µF tantalum is suitable for almost all applications
- Output: minimum 10 µF, with ESR between 0.3 Ω and 22 Ω for stability
- More output capacitance improves stability and transient response
- A protection diode (V_OUT to V_IN) is only needed with very large output capacitance (≥ 1000 µF)
Why 47 µF
- Output (C20, C35): 4.7 × the 10 µF minimum, giving extra margin for stability and better response to load steps such as ESP32 BLE bursts on the 5 V rail
- Input (C19, C34): placed close to each regulator so it has a local, low-impedance supply. This matters because the 7 V rail comes from a switching regulator
- One value for all four: simplifies the bill of materials and assembly
- Well below 1000 µF, so no protection diodes are needed
ESR window
- Electrolytic or tantalum 47 µF capacitors typically have ESR in the 0.3–2 Ω range, inside the 0.3–22 Ω stability window ✅
- Do not substitute 47 µF ceramic (MLCC) capacitors on the outputs. Their ESR is only a few mΩ, below the 0.3 Ω minimum, which can make the LM1117 oscillate
Voltage ratings
| Cap |
Voltage seen |
Minimum rating |
| C19, C34 (input) |
7.2 V |
16 V |
| C20 (5 V output) |
5.1 V |
10 V |
| C35 (3.3 V output) |
3.4 V |
6.3 V (10 V preferred) |
Effect on the buck stage
C19 and C34 sit on the 7 V rail, so they add to the LM2596 output capacitance:
C_7V,total = C5 + C19 + C34 = 220 + 47 + 47 = 314 µF
- Still within the LM2596's 82–820 µF output capacitor range ✅
Ripple rejection
- The LM1117 gives 75 dB typ (60 dB min) rejection at 120 Hz, which strongly attenuates the low-frequency residual ripple on the 7 V rail
- PSRR falls at higher frequencies, so the 150 kHz buck switching ripple is only partly rejected. The 47 µF input and output capacitors help filter it
- The 3.3 V reference rail's tiny constant load keeps it quieter than the 5 V rail
1.65 V Offset (Vref) Generation
Loads on Vref: R12 (33 kΩ, current channel) and R23 (100 kΩ, voltage channel)
Divider (R25, R26)
Vref = 3.3 × R26 / (R25 + R26) = 3.3 × 10k / 20k = 1.65 V
- Equal resistors put Vref exactly at AREF / 2, the centre of the ADC range
- The divider is fed from the same 3.3 V rail as AREF, so Vref is ratiometric: if the 3.3 V rail drifts, Vref drifts in proportion and still lands at mid-scale ADC code (~512)
Why 10 kΩ
I_divider = 3.3 / (10k + 10k) = 165 µA
R_th = R25 || R26 = 5 kΩ
- Low load on the reference rail: 165 µA keeps the 3.3 V rail's load tiny and constant, so the LM1117-3.3 stays well regulated
- Low enough impedance for the op-amp input: TLC082 input bias current is ≤ 50 pA, so the error is 50 pA × 5 kΩ = 0.25 nV, which is negligible
- Lower values (e.g. 1 kΩ) would waste current; much higher values (e.g. 1 MΩ) would pick up more noise and leakage
Resistor tolerance
With 1% resistors: Vref = 1.65 V ± ~1% (worst case ≈ 1.634–1.666 V)
- A Vref error only shifts the DC offset. Firmware subtracts the measured mean, so it has no effect on RMS or power readings
C17: divider filter
C17 sits across R26, forming a low-pass filter with the divider's Thevenin resistance:
fc = 1 / (2π × R_th × C17)
= 1 / (2π × 5k × 100n)
= 318 Hz
| Frequency |
Attenuation |
| 500 Hz |
-5.4 dB |
| 5 kHz |
-24 dB |
| 150 kHz (buck switching) |
-53 dB |
- Filters noise and buck switching ripple coupled onto the 3.3 V rail before it reaches Vref
- Settling time at power-up: τ = 5k × 100n = 0.5 ms, so Vref settles in ~2.5 ms (5τ), well before the firmware starts sampling
- Low-frequency ripple on the 3.3 V rail is already very small after the buck and the LM1117 (75 dB rejection at 120 Hz). Any that remains is ratiometric with AREF, so it largely cancels in the ADC readings
- Optional: 1 µF would lower fc to 32 Hz for stronger filtering, at the cost of ~25 ms settling
C15: rail bypass
- 100 nF ceramic placed at the top of the divider
- Provides a local low-impedance source and shunts high-frequency noise on the 3.3 V rail to ground
- 100 nF is the standard local decoupling value and is effective at the 150 kHz buck switching frequency and above
U8B: voltage follower buffer
Why buffer at all
Without the buffer, the divider's 5 kΩ Thevenin resistance would sit in series with R12 and R23:
R12_eff = 33k + 5k = 38 kΩ vs R11 = 33 kΩ → ~15% mismatch
R23_eff = 100k + 5k = 105 kΩ vs R19 = 100 kΩ → ~5% mismatch
- This would break the matched-ratio difference amplifiers, ruining common-mode rejection and changing the gain
- The two channels would also share the 5 kΩ impedance, so signal current from one channel would modulate Vref for the other (cross-talk)
- The follower's output impedance is close to 0 Ω, so Vref stays stiff and R12/R23 see an ideal voltage source
Operating point
| Check |
Value |
Limit |
OK |
| Input common-mode |
1.65 V |
0 to 3.0 V (V_ICR at 5 V) |
✅ |
| Output |
1.65 V |
0.25 to ~4.1 V swing |
✅ |
| Offset error |
≤ 1.9 mV |
— |
✅ (< 1 LSB) |
| Load current |
µA range (via R12, R23) |
— |
✅ |
C33: not fitted
- A capacitor directly on the output of a unity-gain follower forms a pole with the op-amp's output resistance
- This reduces phase margin. A unity-gain follower is the most vulnerable configuration because it has the highest loop bandwidth (TLC082 GBW = 10 MHz, feedback factor β = 1)
- In testing, fitting C33 caused oscillation on Vref, so it is left empty
- Filtering is already done before the buffer by C17, so C33 isn't needed
- If output filtering is ever required, add a small isolation resistor (e.g. 50–100 Ω) in series between the op-amp output and C33. This decouples the capacitive load from the feedback loop
Summary
| Component |
Value |
Reason |
| V1 |
LM1117-5.0 |
5 V power rail, 1.8 V min headroom over dropout |
| V2 |
LM1117-3.3 |
Separate quiet reference rail for AREF and offset |
| C19, C34 |
47 µF, ≥ 16 V |
Local input bypass from switching 7 V rail |
| C20 |
47 µF, ≥ 10 V |
4.7× datasheet minimum, ESR within 0.3–22 Ω |
| C35 |
47 µF, ≥ 6.3 V |
4.7× datasheet minimum, ESR within 0.3–22 Ω |
| R25, R26 |
10 kΩ |
Vref = 1.65 V, ratiometric with AREF, 165 µA |
| C15 |
100 nF |
Local 3.3 V rail bypass |
| C17 |
100 nF |
318 Hz filter on divider, 2.5 ms settling |
| U8B |
TLC082 follower |
Stiff low-impedance Vref, keeps diff-amp ratios matched |
| C33 |
Not fitted |
Capacitive load caused oscillation |
| Parameter |
Value |
| 5 V dissipation (typical / peak) |
0.18 W / 0.77 W |
| 5 V junction rise (peak) |
~48 °C |
| 3.3 V rail load |
~0.27 mA |
| 3.3 V accuracy |
±1% at 25 °C |
| Vref |
1.65 V ± ~1%, ratiometric |
| 7 V rail total capacitance |
314 µF |
References