NetFPGA 1G CML IP Library - sunnyanthony/NetFPGA-public GitHub Wiki

NetFPGA-10G leverages Xilinx's large AXI-based IP core library and builds all NetFPGA native IP as AXI-compliant pcores. See here for more information on the AXI standard.

IP cores with a "nf10_" or "nf1_cml_" prefix were developed by the NetFPGA team, while those without this prefix were taken or derived from Xilinx IP.

• NetFPGA-1G-CML 1G MAC Interface
• MDIO Control
• AXI4-Stream Packet Generator/Checker
• PCIe DMA Engine
• Input Arbiter
• BRAM Ouput Queues
• NIC Output Port Lookup
• Switch Output Port Lookup
• Router Output Port Lookup
• AXI4-Stream Width Converter