Helium Register, Vectors, Lanes and Elements - stanlytw/CMSIS-NN GitHub Wiki
Helium registers
- Register, Vectors, Lanes and Elements: instruction as VADD.16 q0, q0, q5

A 128-bit Helium vector element sizes and corresponding data type:
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Two 64-bit integers(int64x2, uint64x2)
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Four 32-bit integers or single precision float(int32x4, uint32x4, float32x4)
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Eight 16-bit integers or half precision float(int16x8, uint16x8, float16x8)
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Sixteen 8-bit integers(int8x16, uint8x16)
Predication register
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Let user selectively perform operations on lanes in a vector.
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The predication mask specifies which lanes are processed.