Processor : ARMv7 Processor rev 1 (v7l)
processor : 0
model name : ARMv7 Processor rev 1 (v7l)
BogoMIPS : 48.00
Features : swp half thumb fastmult vfp edsp neon vfpv3 tls vfpv4 idiva idivt vfpd32 evtstrm
CPU implementer : 0x41
CPU architecture: 7
CPU variant : 0x0
CPU part : 0xc0d
CPU revision : 1
processor : 1
model name : ARMv7 Processor rev 1 (v7l)
BogoMIPS : 48.00
Features : swp half thumb fastmult vfp edsp neon vfpv3 tls vfpv4 idiva idivt vfpd32 evtstrm
CPU implementer : 0x41
CPU architecture: 7
CPU variant : 0x0
CPU part : 0xc0d
CPU revision : 1
processor : 2
model name : ARMv7 Processor rev 1 (v7l)
BogoMIPS : 48.00
Features : swp half thumb fastmult vfp edsp neon vfpv3 tls vfpv4 idiva idivt vfpd32 evtstrm
CPU implementer : 0x41
CPU architecture: 7
CPU variant : 0x0
CPU part : 0xc0d
CPU revision : 1
processor : 3
model name : ARMv7 Processor rev 1 (v7l)
BogoMIPS : 48.00
Features : swp half thumb fastmult vfp edsp neon vfpv3 tls vfpv4 idiva idivt vfpd32 evtstrm
CPU implementer : 0x41
CPU architecture: 7
CPU variant : 0x0
CPU part : 0xc0d
CPU revision : 1
Hardware : Rockchip RK3288 (Flattened Device Tree)
Revision : 0000
Serial : 0000000000000000
tinymembench v0.4.9 (simple benchmark for memory throughput and latency)
==========================================================================
== Memory bandwidth tests ==
== ==
== Note 1: 1MB = 1000000 bytes ==
== Note 2: Results for 'copy' tests show how many bytes can be ==
== copied per second (adding together read and writen ==
== bytes would have provided twice higher numbers) ==
== Note 3: 2-pass copy means that we are using a small temporary buffer ==
== to first fetch data into it, and only then write it to the ==
== destination (source -> L1 cache, L1 cache -> destination) ==
== Note 4: If sample standard deviation exceeds 0.1%, it is shown in ==
== brackets ==
==========================================================================
C copy backwards : 2465.8 MB/s
C copy backwards (32 byte blocks) : 2470.9 MB/s
C copy backwards (64 byte blocks) : 2473.7 MB/s
C copy : 1296.6 MB/s (0.2%)
C copy prefetched (32 bytes step) : 1066.8 MB/s (0.3%)
C copy prefetched (64 bytes step) : 1104.8 MB/s (0.9%)
C 2-pass copy : 1437.0 MB/s
C 2-pass copy prefetched (32 bytes step) : 1314.5 MB/s
C 2-pass copy prefetched (64 bytes step) : 1142.0 MB/s (0.6%)
C fill : 3834.9 MB/s (0.2%)
C fill (shuffle within 16 byte blocks) : 3829.6 MB/s (0.2%)
C fill (shuffle within 32 byte blocks) : 3831.9 MB/s (0.2%)
C fill (shuffle within 64 byte blocks) : 3823.9 MB/s (0.1%)
---
standard memcpy : 1699.3 MB/s (0.6%)
standard memset : 3835.3 MB/s
---
NEON read : 4806.1 MB/s
NEON read prefetched (32 bytes step) : 4024.4 MB/s (0.1%)
NEON read prefetched (64 bytes step) : 4489.5 MB/s (0.2%)
NEON read 2 data streams : 4833.5 MB/s
NEON read 2 data streams prefetched (32 bytes step) : 3918.0 MB/s
NEON read 2 data streams prefetched (64 bytes step) : 3925.9 MB/s
NEON copy : 2441.1 MB/s
NEON copy prefetched (32 bytes step) : 2105.0 MB/s (0.7%)
NEON copy prefetched (64 bytes step) : 2056.9 MB/s
NEON unrolled copy : 2409.9 MB/s
NEON unrolled copy prefetched (32 bytes step) : 2182.5 MB/s
NEON unrolled copy prefetched (64 bytes step) : 2396.7 MB/s
NEON copy backwards : 2495.2 MB/s
NEON copy backwards prefetched (32 bytes step) : 1964.7 MB/s (1.6%)
NEON copy backwards prefetched (64 bytes step) : 1815.9 MB/s (0.3%)
NEON 2-pass copy : 1470.0 MB/s
NEON 2-pass copy prefetched (32 bytes step) : 1424.4 MB/s (0.2%)
NEON 2-pass copy prefetched (64 bytes step) : 1252.5 MB/s (0.2%)
NEON unrolled 2-pass copy : 1479.4 MB/s
NEON unrolled 2-pass copy prefetched (32 bytes step) : 1440.7 MB/s (0.1%)
NEON unrolled 2-pass copy prefetched (64 bytes step) : 1519.4 MB/s
NEON fill : 3833.1 MB/s (0.2%)
NEON fill backwards : 3818.3 MB/s
VFP copy : 2408.3 MB/s
VFP 2-pass copy : 1476.1 MB/s
ARM fill (STRD) : 3839.9 MB/s (0.3%)
ARM fill (STM with 8 registers) : 3831.6 MB/s (0.1%)
ARM fill (STM with 4 registers) : 3821.6 MB/s (0.1%)
ARM copy prefetched (incr pld) : 2238.3 MB/s
ARM copy prefetched (wrap pld) : 2190.6 MB/s
ARM 2-pass copy prefetched (incr pld) : 1408.5 MB/s
ARM 2-pass copy prefetched (wrap pld) : 1384.7 MB/s (0.1%)
==========================================================================
== Memory latency test ==
== ==
== Average time is measured for random memory accesses in the buffers ==
== of different sizes. The larger is the buffer, the more significant ==
== are relative contributions of TLB, L1/L2 cache misses and SDRAM ==
== accesses. For extremely large buffer sizes we are expecting to see ==
== page table walk with several requests to SDRAM for almost every ==
== memory access (though 64MiB is not nearly large enough to experience ==
== this effect to its fullest). ==
== ==
== Note 1: All the numbers are representing extra time, which needs to ==
== be added to L1 cache latency. The cycle timings for L1 cache ==
== latency can be usually found in the processor documentation. ==
== Note 2: Dual random read means that we are simultaneously performing ==
== two independent memory accesses at a time. In the case if ==
== the memory subsystem can't handle multiple outstanding ==
== requests, dual random read has the same timings as two ==
== single reads performed one after another. ==
==========================================================================
block size : single random read / dual random read
1024 : 0.0 ns / 0.0 ns
2048 : 0.0 ns / 0.0 ns
4096 : 0.0 ns / 0.0 ns
8192 : 0.0 ns / 0.0 ns
16384 : 0.0 ns / 0.0 ns
32768 : 0.0 ns / 0.0 ns
65536 : 6.9 ns / 11.8 ns
131072 : 10.4 ns / 16.4 ns
262144 : 14.0 ns / 20.0 ns
524288 : 15.9 ns / 21.8 ns
1048576 : 23.0 ns / 32.1 ns
2097152 : 86.0 ns / 125.5 ns
4194304 : 117.4 ns / 153.2 ns
8388608 : 141.0 ns / 172.6 ns
16777216 : 155.0 ns / 184.6 ns
33554432 : 163.5 ns / 192.7 ns
67108864 : 175.6 ns / 207.9 ns