processor : 0
vendor_id : GenuineIntel
cpu family : 6
model : 15
model name : Intel(R) Core(TM)2 Duo CPU T7300 @ 2.00GHz
stepping : 11
microcode : 0xba
cpu MHz : 2000.000
cache size : 4096 KB
physical id : 0
siblings : 2
core id : 0
cpu cores : 2
apicid : 0
initial apicid : 0
fpu : yes
fpu_exception : yes
cpuid level : 10
wp : yes
flags : fpu vme de pse tsc msr pae mce cx8 apic sep mtrr pge mca cmov pat pse36 clflush dts acpi mmx fxsr sse sse2 ss ht tm pbe syscall nx lm constant_tsc arch_perfmon pebs bts rep_good nopl aperfmperf pni dtes64 monitor ds_cpl vmx est tm2 ssse3 cx16 xtpr pdcm lahf_lm ida dts tpr_shadow vnmi flexpriority
bogomips : 3990.01
clflush size : 64
cache_alignment : 64
address sizes : 36 bits physical, 48 bits virtual
power management:
processor : 1
vendor_id : GenuineIntel
cpu family : 6
model : 15
model name : Intel(R) Core(TM)2 Duo CPU T7300 @ 2.00GHz
stepping : 11
microcode : 0xba
cpu MHz : 2000.000
cache size : 4096 KB
physical id : 0
siblings : 2
core id : 1
cpu cores : 2
apicid : 1
initial apicid : 1
fpu : yes
fpu_exception : yes
cpuid level : 10
wp : yes
flags : fpu vme de pse tsc msr pae mce cx8 apic sep mtrr pge mca cmov pat pse36 clflush dts acpi mmx fxsr sse sse2 ss ht tm pbe syscall nx lm constant_tsc arch_perfmon pebs bts rep_good nopl aperfmperf pni dtes64 monitor ds_cpl vmx est tm2 ssse3 cx16 xtpr pdcm lahf_lm ida dts tpr_shadow vnmi flexpriority
bogomips : 3990.01
clflush size : 64
cache_alignment : 64
address sizes : 36 bits physical, 48 bits virtual
power management:
tinymembench v0.3 (simple benchmark for memory throughput and latency)
==========================================================================
== Memory bandwidth tests ==
== ==
== Note 1: 1MB = 1000000 bytes ==
== Note 2: Results for 'copy' tests show how many bytes can be ==
== copied per second (adding together read and writen ==
== bytes would have provided twice higher numbers) ==
== Note 3: 2-pass copy means that we are using a small temporary buffer ==
== to first fetch data into it, and only then write it to the ==
== destination (source -> L1 cache, L1 cache -> destination) ==
== Note 4: If sample standard deviation exceeds 0.1%, it is shown in ==
== brackets ==
==========================================================================
C copy backwards : 1344.7 MB/s
C copy : 1345.3 MB/s
C copy prefetched (32 bytes step) : 1357.2 MB/s (0.4%)
C copy prefetched (64 bytes step) : 1357.0 MB/s
C 2-pass copy : 1249.5 MB/s (0.3%)
C 2-pass copy prefetched (32 bytes step) : 1270.2 MB/s (0.2%)
C 2-pass copy prefetched (64 bytes step) : 1272.9 MB/s (0.3%)
C fill : 1495.2 MB/s
---
standard memcpy : 1951.2 MB/s
standard memset : 3644.8 MB/s
---
SSE2 copy : 1363.9 MB/s
SSE2 nontemporal copy : 1957.1 MB/s
SSE2 copy prefetched (32 bytes step) : 1363.4 MB/s
SSE2 copy prefetched (64 bytes step) : 1363.5 MB/s
SSE2 nontemporal copy prefetched (32 bytes step) : 1961.9 MB/s
SSE2 nontemporal copy prefetched (64 bytes step) : 1957.8 MB/s
SSE2 2-pass copy : 1283.8 MB/s (0.1%)
SSE2 2-pass copy prefetched (32 bytes step) : 1303.2 MB/s (0.3%)
SSE2 2-pass copy prefetched (64 bytes step) : 1300.1 MB/s (0.2%)
SSE2 2-pass nontemporal copy : 968.8 MB/s
SSE2 fill : 1495.2 MB/s
SSE2 nontemporal fill : 3645.2 MB/s
==========================================================================
== Memory latency test ==
== ==
== Average time is measured for random memory accesses in the buffers ==
== of different sizes. The larger is the buffer, the more significant ==
== are relative contributions of TLB, L1/L2 cache misses and SDRAM ==
== accesses. For extremely large buffer sizes we are expecting to see ==
== page table walk with several requests to SDRAM for almost every ==
== memory access (though 64MiB is not nearly large enough to experience ==
== this effect to its fullest). ==
== ==
== Note 1: All the numbers are representing extra time, which needs to ==
== be added to L1 cache latency. The cycle timings for L1 cache ==
== latency can be usually found in the processor documentation. ==
== Note 2: Dual random read means that we are simultaneously performing ==
== two independent memory accesses at a time. In the case if ==
== the memory subsystem can't handle multiple outstanding ==
== requests, dual random read has the same timings as two ==
== single reads performed one after another. ==
==========================================================================
block size : single random read / dual random read, [MADV_NOHUGEPAGE]
1024 : 0.0 ns / 0.0 ns
2048 : 0.0 ns / 0.0 ns
4096 : 0.0 ns / 0.0 ns
8192 : 0.0 ns / 0.0 ns
16384 : 0.0 ns / 0.0 ns
32768 : 0.0 ns / 0.0 ns
65536 : 2.8 ns / 4.6 ns
131072 : 4.7 ns / 6.6 ns
262144 : 5.6 ns / 7.4 ns
524288 : 6.1 ns / 7.9 ns
1048576 : 6.4 ns / 8.1 ns
2097152 : 8.5 ns / 11.1 ns
4194304 : 11.6 ns / 15.5 ns
8388608 : 64.1 ns / 99.3 ns
16777216 : 91.0 ns / 129.3 ns
33554432 : 105.2 ns / 141.9 ns
67108864 : 112.6 ns / 148.1 ns
block size : single random read / dual random read, [MADV_HUGEPAGE]
1024 : 0.0 ns / 0.0 ns
2048 : 0.0 ns / 0.0 ns
4096 : 0.0 ns / 0.0 ns
8192 : 0.0 ns / 0.0 ns
16384 : 0.0 ns / 0.0 ns
32768 : 0.0 ns / 0.0 ns
65536 : 2.8 ns / 4.6 ns
131072 : 4.2 ns / 6.1 ns
262144 : 4.9 ns / 6.6 ns
524288 : 5.2 ns / 6.9 ns
1048576 : 5.4 ns / 7.0 ns
2097152 : 5.4 ns / 7.1 ns
4194304 : 6.9 ns / 7.8 ns
8388608 : 58.4 ns / 88.8 ns
16777216 : 84.9 ns / 113.8 ns
33554432 : 98.2 ns / 123.0 ns
67108864 : 104.8 ns / 126.6 ns