Raspberry Pi (BCM2835) - ssvb/tinymembench GitHub Wiki
processor : 0 model name : ARMv6-compatible processor rev 7 (v6l) BogoMIPS : 2.00 Features : half thumb fastmult vfp edsp java tls CPU implementer : 0x41 CPU architecture: 7 CPU variant : 0x0 CPU part : 0xb76 CPU revision : 7 Hardware : BCM2708 Revision : 0010 Serial : 00000000400b7bc8
The standard 700MHz configuration without any overclocking or config.txt tweaks (2015-01-31-raspbian) and no monitor connected
tinymembench v0.3.9 (simple benchmark for memory throughput and latency)
==========================================================================
== Memory bandwidth tests ==
== ==
== Note 1: 1MB = 1000000 bytes ==
== Note 2: Results for 'copy' tests show how many bytes can be ==
== copied per second (adding together read and writen ==
== bytes would have provided twice higher numbers) ==
== Note 3: 2-pass copy means that we are using a small temporary buffer ==
== to first fetch data into it, and only then write it to the ==
== destination (source -> L1 cache, L1 cache -> destination) ==
== Note 4: If sample standard deviation exceeds 0.1%, it is shown in ==
== brackets ==
==========================================================================
C copy backwards : 127.8 MB/s (1.6%)
C copy : 136.3 MB/s (1.7%)
C copy prefetched (32 bytes step) : 392.6 MB/s
C copy prefetched (64 bytes step) : 392.6 MB/s
C 2-pass copy : 131.6 MB/s
C 2-pass copy prefetched (32 bytes step) : 242.6 MB/s
C 2-pass copy prefetched (64 bytes step) : 242.5 MB/s
C fill : 744.2 MB/s
---
standard memcpy : 387.6 MB/s
standard memset : 1458.5 MB/s
---
VFP copy : 162.3 MB/s
VFP 2-pass copy : 141.2 MB/s
ARM fill (STRD) : 744.4 MB/s
ARM fill (STM with 8 registers) : 1090.7 MB/s
ARM fill (STM with 4 registers) : 1458.4 MB/s
ARM copy prefetched (incr pld) : 387.6 MB/s
ARM copy prefetched (wrap pld) : 207.3 MB/s
ARM 2-pass copy prefetched (incr pld) : 283.3 MB/s
ARM 2-pass copy prefetched (wrap pld) : 229.0 MB/s
==========================================================================
== Memory latency test ==
== ==
== Average time is measured for random memory accesses in the buffers ==
== of different sizes. The larger is the buffer, the more significant ==
== are relative contributions of TLB, L1/L2 cache misses and SDRAM ==
== accesses. For extremely large buffer sizes we are expecting to see ==
== page table walk with several requests to SDRAM for almost every ==
== memory access (though 64MiB is not nearly large enough to experience ==
== this effect to its fullest). ==
== ==
== Note 1: All the numbers are representing extra time, which needs to ==
== be added to L1 cache latency. The cycle timings for L1 cache ==
== latency can be usually found in the processor documentation. ==
== Note 2: Dual random read means that we are simultaneously performing ==
== two independent memory accesses at a time. In the case if ==
== the memory subsystem can't handle multiple outstanding ==
== requests, dual random read has the same timings as two ==
== single reads performed one after another. ==
==========================================================================
block size : single random read / dual random read
1024 : 0.0 ns / 0.0 ns
2048 : 0.0 ns / 0.0 ns
4096 : 0.0 ns / 0.0 ns
8192 : 0.1 ns / 0.1 ns
16384 : 1.7 ns / 2.7 ns
32768 : 32.5 ns / 52.8 ns
65536 : 52.5 ns / 75.5 ns
131072 : 68.5 ns / 92.4 ns
262144 : 133.2 ns / 208.4 ns
524288 : 228.2 ns / 398.5 ns
1048576 : 275.6 ns / 497.1 ns
2097152 : 299.3 ns / 547.6 ns
4194304 : 311.5 ns / 573.4 ns
8388608 : 318.1 ns / 586.8 ns
16777216 : 322.9 ns / 596.9 ns
33554432 : 345.5 ns / 643.6 ns
67108864 : 378.3 ns / 709.9 ns
The standard 700MHz configuration without any overclocking or config.txt tweaks (2015-01-31-raspbian) and a 1920x1080-32@60Hz HDMI monitor connected
tinymembench v0.3.9 (simple benchmark for memory throughput and latency)
==========================================================================
== Memory bandwidth tests ==
== ==
== Note 1: 1MB = 1000000 bytes ==
== Note 2: Results for 'copy' tests show how many bytes can be ==
== copied per second (adding together read and writen ==
== bytes would have provided twice higher numbers) ==
== Note 3: 2-pass copy means that we are using a small temporary buffer ==
== to first fetch data into it, and only then write it to the ==
== destination (source -> L1 cache, L1 cache -> destination) ==
== Note 4: If sample standard deviation exceeds 0.1%, it is shown in ==
== brackets ==
==========================================================================
C copy backwards : 119.3 MB/s (1.7%)
C copy : 127.4 MB/s (1.5%)
C copy prefetched (32 bytes step) : 365.0 MB/s
C copy prefetched (64 bytes step) : 364.9 MB/s
C 2-pass copy : 122.9 MB/s
C 2-pass copy prefetched (32 bytes step) : 226.3 MB/s
C 2-pass copy prefetched (64 bytes step) : 226.3 MB/s
C fill : 692.4 MB/s
---
standard memcpy : 359.6 MB/s
standard memset : 1358.7 MB/s
---
VFP copy : 151.8 MB/s
VFP 2-pass copy : 132.2 MB/s
ARM fill (STRD) : 692.4 MB/s
ARM fill (STM with 8 registers) : 1026.5 MB/s
ARM fill (STM with 4 registers) : 1358.5 MB/s
ARM copy prefetched (incr pld) : 359.7 MB/s
ARM copy prefetched (wrap pld) : 193.0 MB/s
ARM 2-pass copy prefetched (incr pld) : 264.6 MB/s
ARM 2-pass copy prefetched (wrap pld) : 213.2 MB/s
==========================================================================
== Memory latency test ==
== ==
== Average time is measured for random memory accesses in the buffers ==
== of different sizes. The larger is the buffer, the more significant ==
== are relative contributions of TLB, L1/L2 cache misses and SDRAM ==
== accesses. For extremely large buffer sizes we are expecting to see ==
== page table walk with several requests to SDRAM for almost every ==
== memory access (though 64MiB is not nearly large enough to experience ==
== this effect to its fullest). ==
== ==
== Note 1: All the numbers are representing extra time, which needs to ==
== be added to L1 cache latency. The cycle timings for L1 cache ==
== latency can be usually found in the processor documentation. ==
== Note 2: Dual random read means that we are simultaneously performing ==
== two independent memory accesses at a time. In the case if ==
== the memory subsystem can't handle multiple outstanding ==
== requests, dual random read has the same timings as two ==
== single reads performed one after another. ==
==========================================================================
block size : single random read / dual random read
1024 : 0.0 ns / 0.0 ns
2048 : 0.0 ns / 0.0 ns
4096 : 0.0 ns / 0.0 ns
8192 : 0.1 ns / 0.1 ns
16384 : 2.4 ns / 3.9 ns
32768 : 37.0 ns / 60.0 ns
65536 : 58.4 ns / 84.2 ns
131072 : 76.0 ns / 102.9 ns
262144 : 144.9 ns / 226.5 ns
524288 : 246.1 ns / 429.4 ns
1048576 : 296.6 ns / 534.4 ns
2097152 : 322.0 ns / 588.1 ns
4194304 : 334.9 ns / 615.5 ns
8388608 : 341.9 ns / 629.8 ns
16777216 : 352.3 ns / 651.9 ns
33554432 : 372.5 ns / 692.7 ns
67108864 : 410.4 ns / 770.0 ns
cpuinfo:
processor : 0
model name : ARMv6-compatible processor rev 7 (v6l)
BogoMIPS : 2.00
Features : half fastmult vfp edsp java tls
CPU implementer : 0x41
CPU architecture: 7
CPU variant : 0x0
CPU part : 0xb76
CPU revision : 7
Hardware : BCM2708
Revision : 000e
config.txt:
gpu_mem=16
arm_freq=1050
core_freq=500
sdram_freq=600
avoid_pwm_pll=1
over_voltage=6
over_voltage_sdram=6
Results with 1920x1080-32@60Hz HDMI monitor connected:
tinymembench v0.3.9 (simple benchmark for memory throughput and latency)
==========================================================================
== Memory bandwidth tests ==
== ==
== Note 1: 1MB = 1000000 bytes ==
== Note 2: Results for 'copy' tests show how many bytes can be ==
== copied per second (adding together read and writen ==
== bytes would have provided twice higher numbers) ==
== Note 3: 2-pass copy means that we are using a small temporary buffer ==
== to first fetch data into it, and only then write it to the ==
== destination (source -> L1 cache, L1 cache -> destination) ==
== Note 4: If sample standard deviation exceeds 0.1%, it is shown in ==
== brackets ==
==========================================================================
C copy backwards : 213.7 MB/s (11.8%)
C copy : 221.5 MB/s (0.7%)
C copy prefetched (32 bytes step) : 543.5 MB/s
C copy prefetched (64 bytes step) : 543.4 MB/s
C 2-pass copy : 205.5 MB/s
C 2-pass copy prefetched (32 bytes step) : 362.4 MB/s
C 2-pass copy prefetched (64 bytes step) : 362.6 MB/s
C fill : 1068.3 MB/s
---
standard memcpy : 307.9 MB/s
standard memset : 1068.0 MB/s
---
VFP copy : 251.5 MB/s
VFP 2-pass copy : 219.1 MB/s
ARM fill (STRD) : 1068.2 MB/s (0.1%)
ARM fill (STM with 8 registers) : 1834.9 MB/s
ARM fill (STM with 4 registers) : 2083.0 MB/s
ARM copy prefetched (incr pld) : 494.5 MB/s
ARM copy prefetched (wrap pld) : 287.8 MB/s
ARM 2-pass copy prefetched (incr pld) : 431.7 MB/s
ARM 2-pass copy prefetched (wrap pld) : 328.2 MB/s
==========================================================================
== Memory latency test ==
== ==
== Average time is measured for random memory accesses in the buffers ==
== of different sizes. The larger is the buffer, the more significant ==
== are relative contributions of TLB, L1/L2 cache misses and SDRAM ==
== accesses. For extremely large buffer sizes we are expecting to see ==
== page table walk with several requests to SDRAM for almost every ==
== memory access (though 64MiB is not nearly large enough to experience ==
== this effect to its fullest). ==
== ==
== Note 1: All the numbers are representing extra time, which needs to ==
== be added to L1 cache latency. The cycle timings for L1 cache ==
== latency can be usually found in the processor documentation. ==
== Note 2: Dual random read means that we are simultaneously performing ==
== two independent memory accesses at a time. In the case if ==
== the memory subsystem can't handle multiple outstanding ==
== requests, dual random read has the same timings as two ==
== single reads performed one after another. ==
==========================================================================
block size : single random read / dual random read
1024 : 0.0 ns / 0.0 ns
2048 : 0.0 ns / 0.0 ns
4096 : 0.0 ns / 0.0 ns
8192 : 0.1 ns / 0.1 ns
16384 : 1.1 ns / 1.8 ns
32768 : 19.3 ns / 31.3 ns
65536 : 31.2 ns / 44.8 ns
131072 : 41.9 ns / 57.1 ns
262144 : 92.1 ns / 149.4 ns
524288 : 153.7 ns / 272.7 ns
1048576 : 184.5 ns / 336.8 ns
2097152 : 199.9 ns / 369.9 ns
4194304 : 207.6 ns / 386.6 ns
8388608 : 211.5 ns / 395.7 ns
16777216 : 215.2 ns / 403.4 ns
33554432 : 218.3 ns / 410.6 ns
67108864 : 246.3 ns / 466.5 ns
Results with no monitor connected and just minimal framebuffer
tinymembench v0.3.9 (simple benchmark for memory throughput and latency)
==========================================================================
== Memory bandwidth tests ==
== ==
== Note 1: 1MB = 1000000 bytes ==
== Note 2: Results for 'copy' tests show how many bytes can be ==
== copied per second (adding together read and writen ==
== bytes would have provided twice higher numbers) ==
== Note 3: 2-pass copy means that we are using a small temporary buffer ==
== to first fetch data into it, and only then write it to the ==
== destination (source -> L1 cache, L1 cache -> destination) ==
== Note 4: If sample standard deviation exceeds 0.1%, it is shown in ==
== brackets ==
==========================================================================
C copy backwards : 228.8 MB/s (14.4%)
C copy : 236.8 MB/s
C copy prefetched (32 bytes step) : 591.7 MB/s
C copy prefetched (64 bytes step) : 591.5 MB/s
C 2-pass copy : 224.0 MB/s
C 2-pass copy prefetched (32 bytes step) : 397.0 MB/s
C 2-pass copy prefetched (64 bytes step) : 397.0 MB/s
C fill : 1158.0 MB/s
---
standard memcpy : 336.2 MB/s
standard memset : 1158.1 MB/s
---
VFP copy : 273.6 MB/s
VFP 2-pass copy : 237.4 MB/s
ARM fill (STRD) : 1158.0 MB/s
ARM fill (STM with 8 registers) : 1934.4 MB/s
ARM fill (STM with 4 registers) : 2257.4 MB/s
ARM copy prefetched (incr pld) : 540.4 MB/s
ARM copy prefetched (wrap pld) : 314.4 MB/s
ARM 2-pass copy prefetched (incr pld) : 472.5 MB/s
ARM 2-pass copy prefetched (wrap pld) : 360.9 MB/s
==========================================================================
== Memory latency test ==
== ==
== Average time is measured for random memory accesses in the buffers ==
== of different sizes. The larger is the buffer, the more significant ==
== are relative contributions of TLB, L1/L2 cache misses and SDRAM ==
== accesses. For extremely large buffer sizes we are expecting to see ==
== page table walk with several requests to SDRAM for almost every ==
== memory access (though 64MiB is not nearly large enough to experience ==
== this effect to its fullest). ==
== ==
== Note 1: All the numbers are representing extra time, which needs to ==
== be added to L1 cache latency. The cycle timings for L1 cache ==
== latency can be usually found in the processor documentation. ==
== Note 2: Dual random read means that we are simultaneously performing ==
== two independent memory accesses at a time. In the case if ==
== the memory subsystem can't handle multiple outstanding ==
== requests, dual random read has the same timings as two ==
== single reads performed one after another. ==
==========================================================================
block size : single random read / dual random read
1024 : 0.0 ns / 0.0 ns
2048 : 0.0 ns / 0.0 ns
4096 : 0.0 ns / 0.0 ns
8192 : 0.0 ns / 0.0 ns
16384 : 0.6 ns / 1.0 ns
32768 : 17.0 ns / 27.6 ns
65536 : 28.1 ns / 40.2 ns
131072 : 36.4 ns / 49.0 ns
262144 : 84.4 ns / 136.7 ns
524288 : 143.4 ns / 254.2 ns
1048576 : 173.1 ns / 316.0 ns
2097152 : 188.1 ns / 347.8 ns
4194304 : 195.7 ns / 364.0 ns
8388608 : 199.8 ns / 372.9 ns
16777216 : 203.7 ns / 381.0 ns
33554432 : 216.8 ns / 407.2 ns
67108864 : 244.3 ns / 462.5 ns