P&W R619AC (Qualcomm Atheros IPQ4019, OC) - ssvb/tinymembench GitHub Wiki
Device: P&W R619AC, OpenWRT 23.05.3
CONFIG_EXTRA_OPTIMIZATION="-pipe -O3 -mtune=cortex-a7"
Overclocked: 717 -> 896MHz CPU core
# uname -a
Linux R619AC 5.15.150 #0 SMP Fri Mar 22 22:09:42 2024 armv7l GNU/Linux
# mhz
count=211565 us50=12196 us250=59461 diff=47265 cpu_MHz=895.229
# cat /proc/cpuinfo
...
processor : 3
model name : ARMv7 Processor rev 5 (v7l)
BogoMIPS : 120.13
Features : half thumb fastmult vfp edsp neon vfpv3 tls vfpv4 idiva idivt vfpd32 lpae evtstrm
CPU implementer : 0x41
CPU architecture: 7
CPU variant : 0x0
CPU part : 0xc07
CPU revision : 5
Hardware : Generic DT based system
Revision : 0000
Serial : 0000000000000000
# tinymembench
tinymembench v0.4.9 (simple benchmark for memory throughput and latency)
==========================================================================
== Memory bandwidth tests ==
== ==
== Note 1: 1MB = 1000000 bytes ==
== Note 2: Results for 'copy' tests show how many bytes can be ==
== copied per second (adding together read and writen ==
== bytes would have provided twice higher numbers) ==
== Note 3: 2-pass copy means that we are using a small temporary buffer ==
== to first fetch data into it, and only then write it to the ==
== destination (source -> L1 cache, L1 cache -> destination) ==
== Note 4: If sample standard deviation exceeds 0.1%, it is shown in ==
== brackets ==
==========================================================================
C copy backwards : 220.6 MB/s (0.9%)
C copy backwards (32 byte blocks) : 809.4 MB/s (0.8%)
C copy backwards (64 byte blocks) : 815.8 MB/s (0.9%)
C copy : 845.7 MB/s (1.1%)
C copy prefetched (32 bytes step) : 925.6 MB/s (1.0%)
C copy prefetched (64 bytes step) : 974.8 MB/s (1.3%)
C 2-pass copy : 659.3 MB/s (0.6%)
C 2-pass copy prefetched (32 bytes step) : 712.5 MB/s (0.5%)
C 2-pass copy prefetched (64 bytes step) : 792.6 MB/s (0.6%)
C fill : 2421.7 MB/s (0.6%)
C fill (shuffle within 16 byte blocks) : 2428.4 MB/s (0.8%)
C fill (shuffle within 32 byte blocks) : 441.4 MB/s (0.9%)
C fill (shuffle within 64 byte blocks) : 466.6 MB/s (1.3%)
---
standard memcpy : 903.7 MB/s (0.7%)
standard memset : 2352.0 MB/s (0.7%)
---
NEON read : 1515.6 MB/s (0.5%)
NEON read prefetched (32 bytes step) : 1668.3 MB/s (0.7%)
NEON read prefetched (64 bytes step) : 1643.4 MB/s (0.7%)
NEON read 2 data streams : 449.2 MB/s (0.6%)
NEON read 2 data streams prefetched (32 bytes step) : 823.5 MB/s (0.7%)
NEON read 2 data streams prefetched (64 bytes step) : 912.0 MB/s (0.7%)
NEON copy : 907.7 MB/s (1.5%)
NEON copy prefetched (32 bytes step) : 898.9 MB/s (1.2%)
NEON copy prefetched (64 bytes step) : 977.0 MB/s (1.2%)
NEON unrolled copy : 884.4 MB/s (0.9%)
NEON unrolled copy prefetched (32 bytes step) : 922.1 MB/s (1.2%)
NEON unrolled copy prefetched (64 bytes step) : 960.0 MB/s (1.0%)
NEON copy backwards : 885.7 MB/s (1.1%)
NEON copy backwards prefetched (32 bytes step) : 871.9 MB/s (0.8%)
NEON copy backwards prefetched (64 bytes step) : 935.7 MB/s (1.5%)
NEON 2-pass copy : 823.0 MB/s (0.8%)
NEON 2-pass copy prefetched (32 bytes step) : 863.6 MB/s (0.9%)
NEON 2-pass copy prefetched (64 bytes step) : 867.3 MB/s (0.9%)
NEON unrolled 2-pass copy : 649.4 MB/s (0.6%)
NEON unrolled 2-pass copy prefetched (32 bytes step) : 630.4 MB/s (0.3%)
NEON unrolled 2-pass copy prefetched (64 bytes step) : 679.6 MB/s (0.5%)
NEON fill : 2413.9 MB/s (0.4%)
NEON fill backwards : 2420.3 MB/s (0.7%)
VFP copy : 887.1 MB/s (0.7%)
VFP 2-pass copy : 698.8 MB/s (0.6%)
ARM fill (STRD) : 2076.2 MB/s (5.6%)
ARM fill (STM with 8 registers) : 2431.9 MB/s (1.2%)
ARM fill (STM with 4 registers) : 2424.6 MB/s (0.6%)
ARM copy prefetched (incr pld) : 930.3 MB/s (1.0%)
ARM copy prefetched (wrap pld) : 922.2 MB/s (2.2%)
ARM 2-pass copy prefetched (incr pld) : 753.4 MB/s (1.1%)
ARM 2-pass copy prefetched (wrap pld) : 767.8 MB/s (0.9%)
==========================================================================
== Memory latency test ==
== ==
== Average time is measured for random memory accesses in the buffers ==
== of different sizes. The larger is the buffer, the more significant ==
== are relative contributions of TLB, L1/L2 cache misses and SDRAM ==
== accesses. For extremely large buffer sizes we are expecting to see ==
== page table walk with several requests to SDRAM for almost every ==
== memory access (though 64MiB is not nearly large enough to experience ==
== this effect to its fullest). ==
== ==
== Note 1: All the numbers are representing extra time, which needs to ==
== be added to L1 cache latency. The cycle timings for L1 cache ==
== latency can be usually found in the processor documentation. ==
== Note 2: Dual random read means that we are simultaneously performing ==
== two independent memory accesses at a time. In the case if ==
== the memory subsystem can't handle multiple outstanding ==
== requests, dual random read has the same timings as two ==
== single reads performed one after another. ==
==========================================================================
block size : single random read / dual random read
1024 : 0.0 ns / 0.1 ns
2048 : 0.0 ns / 0.1 ns
4096 : 0.0 ns / 0.0 ns
8192 : 0.0 ns / 0.0 ns
16384 : 0.0 ns / 0.0 ns
32768 : 0.0 ns / 0.0 ns
65536 : 7.0 ns / 12.4 ns
131072 : 11.5 ns / 18.0 ns
262144 : 20.6 ns / 31.9 ns
524288 : 68.8 ns / 107.1 ns
1048576 : 94.7 ns / 133.6 ns
2097152 : 114.8 ns / 151.8 ns
4194304 : 125.5 ns / 160.7 ns
8388608 : 133.5 ns / 167.9 ns
16777216 : 141.5 ns / 177.6 ns
33554432 : 152.3 ns / 198.0 ns
67108864 : 170.4 ns / 234.1 ns