Orange Pi PC (Allwinner H3) - ssvb/tinymembench GitHub Wiki
Running at 1.2 GHz, the rated frequency of the SoC:
Processor : ARMv7 Processor rev 5 (v7l) processor : 0 BogoMIPS : 4800.00 processor : 1 BogoMIPS : 4800.00 processor : 2 BogoMIPS : 4800.00 processor : 3 BogoMIPS : 4800.00 Features : swp half thumb fastmult vfp edsp thumbee neon vfpv3 tls vfpv4 idiva idivt CPU implementer : 0x41 CPU architecture: 7 CPU variant : 0x0 CPU part : 0xc07 CPU revision : 5 Hardware : sun8i Revision : 0000
tinymembench v0.4.9 (simple benchmark for memory throughput and latency)
==========================================================================
== Memory bandwidth tests ==
== ==
== Note 1: 1MB = 1000000 bytes ==
== Note 2: Results for 'copy' tests show how many bytes can be ==
== copied per second (adding together read and writen ==
== bytes would have provided twice higher numbers) ==
== Note 3: 2-pass copy means that we are using a small temporary buffer ==
== to first fetch data into it, and only then write it to the ==
== destination (source -> L1 cache, L1 cache -> destination) ==
== Note 4: If sample standard deviation exceeds 0.1%, it is shown in ==
== brackets ==
==========================================================================
C copy backwards : 259.5 MB/s
C copy backwards (32 byte blocks) : 1019.4 MB/s
C copy backwards (64 byte blocks) : 1041.3 MB/s
C copy : 1016.1 MB/s
C copy prefetched (32 bytes step) : 909.0 MB/s
C copy prefetched (64 bytes step) : 1044.8 MB/s
C 2-pass copy : 791.9 MB/s
C 2-pass copy prefetched (32 bytes step) : 785.3 MB/s
C 2-pass copy prefetched (64 bytes step) : 820.6 MB/s
C fill : 3843.9 MB/s
C fill (shuffle within 16 byte blocks) : 3843.7 MB/s
C fill (shuffle within 32 byte blocks) : 315.8 MB/s
C fill (shuffle within 64 byte blocks) : 319.1 MB/s
---
standard memcpy : 876.7 MB/s
standard memset : 3035.7 MB/s
---
NEON read : 1350.2 MB/s
NEON read prefetched (32 bytes step) : 1550.7 MB/s
NEON read prefetched (64 bytes step) : 1553.0 MB/s
NEON read 2 data streams : 384.6 MB/s
NEON read 2 data streams prefetched (32 bytes step) : 730.7 MB/s
NEON read 2 data streams prefetched (64 bytes step) : 775.4 MB/s
NEON copy : 1035.4 MB/s
NEON copy prefetched (32 bytes step) : 1061.5 MB/s
NEON copy prefetched (64 bytes step) : 1200.8 MB/s
NEON unrolled copy : 1035.8 MB/s
NEON unrolled copy prefetched (32 bytes step) : 1090.2 MB/s
NEON unrolled copy prefetched (64 bytes step) : 1135.1 MB/s
NEON copy backwards : 1020.3 MB/s
NEON copy backwards prefetched (32 bytes step) : 1027.9 MB/s
NEON copy backwards prefetched (64 bytes step) : 1154.0 MB/s
NEON 2-pass copy : 888.7 MB/s
NEON 2-pass copy prefetched (32 bytes step) : 950.7 MB/s
NEON 2-pass copy prefetched (64 bytes step) : 983.6 MB/s
NEON unrolled 2-pass copy : 783.2 MB/s
NEON unrolled 2-pass copy prefetched (32 bytes step) : 737.6 MB/s
NEON unrolled 2-pass copy prefetched (64 bytes step) : 786.8 MB/s
NEON fill : 3843.5 MB/s
NEON fill backwards : 3841.4 MB/s
VFP copy : 1044.0 MB/s
VFP 2-pass copy : 781.6 MB/s
ARM fill (STRD) : 3036.4 MB/s
ARM fill (STM with 8 registers) : 3844.0 MB/s
ARM fill (STM with 4 registers) : 3559.2 MB/s
ARM copy prefetched (incr pld) : 1141.2 MB/s
ARM copy prefetched (wrap pld) : 1019.6 MB/s
ARM 2-pass copy prefetched (incr pld) : 885.1 MB/s
ARM 2-pass copy prefetched (wrap pld) : 837.7 MB/s
==========================================================================
== Memory latency test ==
== ==
== Average time is measured for random memory accesses in the buffers ==
== of different sizes. The larger is the buffer, the more significant ==
== are relative contributions of TLB, L1/L2 cache misses and SDRAM ==
== accesses. For extremely large buffer sizes we are expecting to see ==
== page table walk with several requests to SDRAM for almost every ==
== memory access (though 64MiB is not nearly large enough to experience ==
== this effect to its fullest). ==
== ==
== Note 1: All the numbers are representing extra time, which needs to ==
== be added to L1 cache latency. The cycle timings for L1 cache ==
== latency can be usually found in the processor documentation. ==
== Note 2: Dual random read means that we are simultaneously performing ==
== two independent memory accesses at a time. In the case if ==
== the memory subsystem can't handle multiple outstanding ==
== requests, dual random read has the same timings as two ==
== single reads performed one after another. ==
==========================================================================
block size : single random read / dual random read
1024 : 0.0 ns / 0.0 ns
2048 : 0.0 ns / 0.0 ns
4096 : 0.0 ns / 0.0 ns
8192 : 0.0 ns / 0.0 ns
16384 : 0.0 ns / 0.0 ns
32768 : 0.0 ns / 0.0 ns
65536 : 5.2 ns / 9.1 ns
131072 : 34.5 ns / 62.0 ns
262144 : 106.0 ns / 158.5 ns
524288 : 115.4 ns / 167.6 ns
1048576 : 136.5 ns / 185.3 ns
2097152 : 152.7 ns / 199.2 ns
4194304 : 159.8 ns / 197.7 ns
8388608 : 164.5 ns / 208.0 ns
16777216 : 170.0 ns / 207.9 ns
33554432 : 175.6 ns / 220.5 ns
67108864 : 186.8 ns / 235.4 ns