OMAP5 uEVM (OMAP5432) - ssvb/tinymembench GitHub Wiki
OMAP5 uEVM (rev G)
Texas Instruments OMAP5432 es2.0 SoC
dual-core ARM Cortex-A15 r2p2 @ 1.5 GHz
2 MiB unified L2 cache (2048 sets × 16 ways × 64 bytes)
128-bit AXI4 interface @ cpu/2 (750 MHz)
two 32-bit DDR3-1066 memory interfaces
tinymembench v0.4.9 (simple benchmark for memory throughput and latency)
==========================================================================
== Memory bandwidth tests ==
== ==
== Note 1: 1MB = 1000000 bytes ==
== Note 2: Results for 'copy' tests show how many bytes can be ==
== copied per second (adding together read and writen ==
== bytes would have provided twice higher numbers) ==
== Note 3: 2-pass copy means that we are using a small temporary buffer ==
== to first fetch data into it, and only then write it to the ==
== destination (source -> L1 cache, L1 cache -> destination) ==
== Note 4: If sample standard deviation exceeds 0.1%, it is shown in ==
== brackets ==
==========================================================================
C copy backwards : 1210.2 MB/s
C copy backwards (32 byte blocks) : 1203.3 MB/s (0.1%)
C copy backwards (64 byte blocks) : 2303.2 MB/s
C copy : 2391.6 MB/s (0.1%)
C copy prefetched (32 bytes step) : 1370.4 MB/s
C copy prefetched (64 bytes step) : 1374.4 MB/s
C 2-pass copy : 1415.3 MB/s
C 2-pass copy prefetched (32 bytes step) : 1235.8 MB/s
C 2-pass copy prefetched (64 bytes step) : 1237.5 MB/s
C fill : 5815.9 MB/s (0.2%)
C fill (shuffle within 16 byte blocks) : 1614.1 MB/s
C fill (shuffle within 32 byte blocks) : 1613.4 MB/s
C fill (shuffle within 64 byte blocks) : 1607.1 MB/s
---
standard memcpy : 2191.4 MB/s
standard memset : 5793.8 MB/s (0.2%)
---
NEON read : 3451.1 MB/s
NEON read prefetched (32 bytes step) : 4227.0 MB/s
NEON read prefetched (64 bytes step) : 4231.6 MB/s
NEON read 2 data streams : 3548.7 MB/s
NEON read 2 data streams prefetched (32 bytes step) : 4335.2 MB/s
NEON read 2 data streams prefetched (64 bytes step) : 4335.3 MB/s
NEON copy : 2425.9 MB/s
NEON copy prefetched (32 bytes step) : 2489.1 MB/s
NEON copy prefetched (64 bytes step) : 2488.7 MB/s
NEON unrolled copy : 2194.3 MB/s
NEON unrolled copy prefetched (32 bytes step) : 2512.9 MB/s
NEON unrolled copy prefetched (64 bytes step) : 2513.9 MB/s
NEON copy backwards : 1218.0 MB/s
NEON copy backwards prefetched (32 bytes step) : 1367.1 MB/s (0.1%)
NEON copy backwards prefetched (64 bytes step) : 1367.1 MB/s
NEON 2-pass copy : 2082.7 MB/s
NEON 2-pass copy prefetched (32 bytes step) : 2288.3 MB/s
NEON 2-pass copy prefetched (64 bytes step) : 2289.4 MB/s
NEON unrolled 2-pass copy : 1439.5 MB/s (0.3%)
NEON unrolled 2-pass copy prefetched (32 bytes step) : 1814.1 MB/s (0.8%)
NEON unrolled 2-pass copy prefetched (64 bytes step) : 1853.6 MB/s (0.5%)
NEON fill : 5805.3 MB/s (0.3%)
NEON fill backwards : 1615.7 MB/s
VFP copy : 2350.7 MB/s
VFP 2-pass copy : 1377.4 MB/s
ARM fill (STRD) : 5793.7 MB/s (0.2%)
ARM fill (STM with 8 registers) : 5773.3 MB/s
ARM fill (STM with 4 registers) : 5780.1 MB/s
ARM copy prefetched (incr pld) : 2485.3 MB/s
ARM copy prefetched (wrap pld) : 2444.4 MB/s
ARM 2-pass copy prefetched (incr pld) : 1658.0 MB/s
ARM 2-pass copy prefetched (wrap pld) : 1620.9 MB/s
==========================================================================
== Memory latency test ==
== ==
== Average time is measured for random memory accesses in the buffers ==
== of different sizes. The larger is the buffer, the more significant ==
== are relative contributions of TLB, L1/L2 cache misses and SDRAM ==
== accesses. For extremely large buffer sizes we are expecting to see ==
== page table walk with several requests to SDRAM for almost every ==
== memory access (though 64MiB is not nearly large enough to experience ==
== this effect to its fullest). ==
== ==
== Note 1: All the numbers are representing extra time, which needs to ==
== be added to L1 cache latency. The cycle timings for L1 cache ==
== latency can be usually found in the processor documentation. ==
== Note 2: Dual random read means that we are simultaneously performing ==
== two independent memory accesses at a time. In the case if ==
== the memory subsystem can't handle multiple outstanding ==
== requests, dual random read has the same timings as two ==
== single reads performed one after another. ==
==========================================================================
block size : single random read / dual random read
1024 : 0.0 ns / 0.0 ns
2048 : 0.0 ns / 0.0 ns
4096 : 0.0 ns / 0.1 ns
8192 : 0.0 ns / 0.1 ns
16384 : 0.0 ns / 0.0 ns
32768 : 0.0 ns / 0.1 ns
65536 : 5.2 ns / 8.2 ns
131072 : 8.0 ns / 11.0 ns
262144 : 11.6 ns / 14.7 ns
524288 : 13.4 ns / 16.9 ns
1048576 : 14.5 ns / 18.1 ns
2097152 : 19.4 ns / 24.8 ns
4194304 : 90.7 ns / 138.6 ns
8388608 : 127.1 ns / 178.9 ns
16777216 : 145.8 ns / 197.3 ns
33554432 : 156.4 ns / 208.8 ns
67108864 : 171.7 ns / 234.6 ns
tinymembench v0.4.9 (simple benchmark for memory throughput and latency)
==========================================================================
== Memory bandwidth tests ==
== ==
== Note 1: 1MB = 1000000 bytes ==
== Note 2: Results for 'copy' tests show how many bytes can be ==
== copied per second (adding together read and writen ==
== bytes would have provided twice higher numbers) ==
== Note 3: 2-pass copy means that we are using a small temporary buffer ==
== to first fetch data into it, and only then write it to the ==
== destination (source -> L1 cache, L1 cache -> destination) ==
== Note 4: If sample standard deviation exceeds 0.1%, it is shown in ==
== brackets ==
==========================================================================
C copy backwards : 1101.8 MB/s
C copy backwards (32 byte blocks) : 1096.8 MB/s (0.3%)
C copy backwards (64 byte blocks) : 2162.1 MB/s
C copy : 2232.3 MB/s
C copy prefetched (32 bytes step) : 1263.7 MB/s (0.2%)
C copy prefetched (64 bytes step) : 1265.4 MB/s
C 2-pass copy : 1244.1 MB/s
C 2-pass copy prefetched (32 bytes step) : 1116.2 MB/s
C 2-pass copy prefetched (64 bytes step) : 1117.0 MB/s
C fill : 3836.8 MB/s
C fill (shuffle within 16 byte blocks) : 1519.5 MB/s (0.2%)
C fill (shuffle within 32 byte blocks) : 1519.1 MB/s
C fill (shuffle within 64 byte blocks) : 1508.6 MB/s (0.1%)
---
standard memcpy : 1932.0 MB/s (0.4%)
standard memset : 3794.5 MB/s (0.3%)
---
NEON read : 2843.5 MB/s
NEON read prefetched (32 bytes step) : 3487.2 MB/s
NEON read prefetched (64 bytes step) : 3499.9 MB/s
NEON read 2 data streams : 2896.9 MB/s
NEON read 2 data streams prefetched (32 bytes step) : 3595.4 MB/s (0.3%)
NEON read 2 data streams prefetched (64 bytes step) : 3597.6 MB/s
NEON copy : 2285.8 MB/s
NEON copy prefetched (32 bytes step) : 2407.3 MB/s
NEON copy prefetched (64 bytes step) : 2407.3 MB/s
NEON unrolled copy : 2039.2 MB/s (0.3%)
NEON unrolled copy prefetched (32 bytes step) : 2403.3 MB/s
NEON unrolled copy prefetched (64 bytes step) : 2417.1 MB/s
NEON copy backwards : 1114.5 MB/s
NEON copy backwards prefetched (32 bytes step) : 1257.1 MB/s
NEON copy backwards prefetched (64 bytes step) : 1257.2 MB/s
NEON 2-pass copy : 1610.4 MB/s
NEON 2-pass copy prefetched (32 bytes step) : 1826.6 MB/s (0.3%)
NEON 2-pass copy prefetched (64 bytes step) : 1831.1 MB/s (0.1%)
NEON unrolled 2-pass copy : 1290.7 MB/s (0.9%)
NEON unrolled 2-pass copy prefetched (32 bytes step) : 1549.9 MB/s (1.0%)
NEON unrolled 2-pass copy prefetched (64 bytes step) : 1599.2 MB/s (1.1%)
NEON fill : 3814.3 MB/s (0.6%)
NEON fill backwards : 1519.1 MB/s (0.2%)
VFP copy : 2148.3 MB/s
VFP 2-pass copy : 1207.5 MB/s
ARM fill (STRD) : 3797.0 MB/s
ARM fill (STM with 8 registers) : 3818.1 MB/s (0.2%)
ARM fill (STM with 4 registers) : 3835.9 MB/s (0.2%)
ARM copy prefetched (incr pld) : 2397.7 MB/s
ARM copy prefetched (wrap pld) : 2286.6 MB/s
ARM 2-pass copy prefetched (incr pld) : 1442.2 MB/s
ARM 2-pass copy prefetched (wrap pld) : 1386.1 MB/s
==========================================================================
== Memory latency test ==
== ==
== Average time is measured for random memory accesses in the buffers ==
== of different sizes. The larger is the buffer, the more significant ==
== are relative contributions of TLB, L1/L2 cache misses and SDRAM ==
== accesses. For extremely large buffer sizes we are expecting to see ==
== page table walk with several requests to SDRAM for almost every ==
== memory access (though 64MiB is not nearly large enough to experience ==
== this effect to its fullest). ==
== ==
== Note 1: All the numbers are representing extra time, which needs to ==
== be added to L1 cache latency. The cycle timings for L1 cache ==
== latency can be usually found in the processor documentation. ==
== Note 2: Dual random read means that we are simultaneously performing ==
== two independent memory accesses at a time. In the case if ==
== the memory subsystem can't handle multiple outstanding ==
== requests, dual random read has the same timings as two ==
== single reads performed one after another. ==
==========================================================================
block size : single random read / dual random read
1024 : 0.0 ns / 0.0 ns
2048 : 0.0 ns / 0.1 ns
4096 : 0.0 ns / 0.0 ns
8192 : 0.0 ns / 0.0 ns
16384 : 0.0 ns / 0.0 ns
32768 : 0.0 ns / 0.0 ns
65536 : 7.9 ns / 12.1 ns
131072 : 12.1 ns / 16.2 ns
262144 : 17.4 ns / 21.9 ns
524288 : 20.1 ns / 25.2 ns
1048576 : 21.6 ns / 27.0 ns
2097152 : 27.6 ns / 35.6 ns
4194304 : 109.6 ns / 166.9 ns
8388608 : 151.3 ns / 216.9 ns
16777216 : 172.9 ns / 241.2 ns
33554432 : 185.0 ns / 256.2 ns
67108864 : 205.3 ns / 291.6 ns