ODROID XU4 (Exynos 5422 based SoC) - ssvb/tinymembench GitHub Wiki
1. Tinymembench compiling parameters:
make, orCFLAGS="-O3 -march=native -mcpu=cortex-a15.cortex-a7 -mtune=cortex-a15.cortex-a7 -mfpu=neon-vfpv4 -mfloat-abi=hard -fomit-frame-pointer -ffast-math" make, or- similars, like only
CFLAGS="-O3 -march=native -mcpu=cortex-a15.cortex-a7", CFLAGS="-O3 -march=native -mcpu=cortex-a15", etc
doesn't produce any considerable performance benefit; therefore just type make and don't waste your time with CFLAGS parameters.
2. The tinymembench test itself:
root@hiperborea ~/tinymembench-master # ./tinymembench
tinymembench v0.4.9 (simple benchmark for memory throughput and latency)
==========================================================================
== Memory bandwidth tests ==
== ==
== Note 1: 1MB = 1000000 bytes ==
== Note 2: Results for 'copy' tests show how many bytes can be ==
== copied per second (adding together read and writen ==
== bytes would have provided twice higher numbers) ==
== Note 3: 2-pass copy means that we are using a small temporary buffer ==
== to first fetch data into it, and only then write it to the ==
== destination (source -> L1 cache, L1 cache -> destination) ==
== Note 4: If sample standard deviation exceeds 0.1%, it is shown in ==
== brackets ==
==========================================================================
C copy backwards : 1165.7 MB/s
C copy backwards (32 byte blocks) : 1155.1 MB/s
C copy backwards (64 byte blocks) : 2280.3 MB/s (0.4%)
C copy : 2440.1 MB/s
C copy prefetched (32 bytes step) : 2746.1 MB/s
C copy prefetched (64 bytes step) : 2820.6 MB/s
C 2-pass copy : 1355.5 MB/s
C 2-pass copy prefetched (32 bytes step) : 1614.1 MB/s
C 2-pass copy prefetched (64 bytes step) : 1636.7 MB/s
C fill : 4907.6 MB/s (0.9%)
C fill (shuffle within 16 byte blocks) : 1817.8 MB/s
C fill (shuffle within 32 byte blocks) : 1817.8 MB/s
C fill (shuffle within 64 byte blocks) : 1915.2 MB/s
---
standard memcpy : 2255.2 MB/s (0.2%)
standard memset : 4913.1 MB/s (0.9%)
---
NEON read : 3387.6 MB/s
NEON read prefetched (32 bytes step) : 4265.2 MB/s
NEON read prefetched (64 bytes step) : 4267.1 MB/s
NEON read 2 data streams : 3447.4 MB/s
NEON read 2 data streams prefetched (32 bytes step) : 4419.4 MB/s
NEON read 2 data streams prefetched (64 bytes step) : 4425.6 MB/s
NEON copy : 2655.9 MB/s
NEON copy prefetched (32 bytes step) : 2986.1 MB/s
NEON copy prefetched (64 bytes step) : 2978.4 MB/s
NEON unrolled copy : 2307.7 MB/s
NEON unrolled copy prefetched (32 bytes step) : 3324.5 MB/s
NEON unrolled copy prefetched (64 bytes step) : 3344.9 MB/s (0.2%)
NEON copy backwards : 1239.2 MB/s
NEON copy backwards prefetched (32 bytes step) : 1438.0 MB/s
NEON copy backwards prefetched (64 bytes step) : 1438.1 MB/s
NEON 2-pass copy : 2091.1 MB/s
NEON 2-pass copy prefetched (32 bytes step) : 2221.2 MB/s
NEON 2-pass copy prefetched (64 bytes step) : 2222.7 MB/s
NEON unrolled 2-pass copy : 1420.1 MB/s
NEON unrolled 2-pass copy prefetched (32 bytes step) : 1764.7 MB/s
NEON unrolled 2-pass copy prefetched (64 bytes step) : 1780.6 MB/s
NEON fill : 4905.0 MB/s (0.9%)
NEON fill backwards : 1831.1 MB/s (0.8%)
VFP copy : 2431.4 MB/s
VFP 2-pass copy : 1337.2 MB/s
ARM fill (STRD) : 4900.0 MB/s (8.5%)
ARM fill (STM with 8 registers) : 4918.4 MB/s (0.4%)
ARM fill (STM with 4 registers) : 4919.6 MB/s (0.7%)
ARM copy prefetched (incr pld) : 2921.1 MB/s (0.2%)
ARM copy prefetched (wrap pld) : 2743.5 MB/s
ARM 2-pass copy prefetched (incr pld) : 1663.7 MB/s
ARM 2-pass copy prefetched (wrap pld) : 1638.5 MB/s
==========================================================================
== Memory latency test ==
== ==
== Average time is measured for random memory accesses in the buffers ==
== of different sizes. The larger is the buffer, the more significant ==
== are relative contributions of TLB, L1/L2 cache misses and SDRAM ==
== accesses. For extremely large buffer sizes we are expecting to see ==
== page table walk with several requests to SDRAM for almost every ==
== memory access (though 64MiB is not nearly large enough to experience ==
== this effect to its fullest). ==
== ==
== Note 1: All the numbers are representing extra time, which needs to ==
== be added to L1 cache latency. The cycle timings for L1 cache ==
== latency can be usually found in the processor documentation. ==
== Note 2: Dual random read means that we are simultaneously performing ==
== two independent memory accesses at a time. In the case if ==
== the memory subsystem can't handle multiple outstanding ==
== requests, dual random read has the same timings as two ==
== single reads performed one after another. ==
==========================================================================
block size : single random read / dual random read
1024 : 0.0 ns / 0.1 ns
2048 : 0.0 ns / 0.1 ns
4096 : 0.0 ns / 0.1 ns
8192 : 0.0 ns / 0.1 ns
16384 : 0.0 ns / 0.1 ns
32768 : 0.0 ns / 0.1 ns
65536 : 4.4 ns / 6.9 ns
131072 : 6.7 ns / 9.1 ns
262144 : 9.6 ns / 12.0 ns
524288 : 11.0 ns / 13.6 ns
1048576 : 12.0 ns / 14.6 ns
2097152 : 26.6 ns / 40.3 ns
4194304 : 94.8 ns / 142.7 ns
8388608 : 132.8 ns / 181.7 ns
16777216 : 152.6 ns / 198.2 ns
33554432 : 167.5 ns / 218.4 ns
67108864 : 176.6 ns / 235.2 ns
3. Why the test again in Exynos-5422 based SoC?
-
These results are almost practically the same like as the ODROID XU3, already tested with tinymembench
-
This new page ODROID-XU4 was created here in order to have a test by device more than for CPU-SoC, thus is good to know or find out, that our presumption, in this matter, performs equal on both Samsung Exynos 5422 SoC devices.