ODROID XU3 (Exynos 5422) - ssvb/tinymembench GitHub Wiki
processor : 0 model name : ARMv7 Processor rev 3 (v7l) BogoMIPS : 78.00 Features : swp half thumb fastmult vfp edsp neon vfpv3 tls vfpv4 idiva idivt CPU implementer : 0x41 CPU architecture: 7 CPU variant : 0x0 CPU part : 0xc07 CPU revision : 3 processor : 1 model name : ARMv7 Processor rev 3 (v7l) BogoMIPS : 78.00 Features : swp half thumb fastmult vfp edsp neon vfpv3 tls vfpv4 idiva idivt CPU implementer : 0x41 CPU architecture: 7 CPU variant : 0x0 CPU part : 0xc07 CPU revision : 3 processor : 2 model name : ARMv7 Processor rev 3 (v7l) BogoMIPS : 78.00 Features : swp half thumb fastmult vfp edsp neon vfpv3 tls vfpv4 idiva idivt CPU implementer : 0x41 CPU architecture: 7 CPU variant : 0x0 CPU part : 0xc07 CPU revision : 3 processor : 3 model name : ARMv7 Processor rev 3 (v7l) BogoMIPS : 78.00 Features : swp half thumb fastmult vfp edsp neon vfpv3 tls vfpv4 idiva idivt CPU implementer : 0x41 CPU architecture: 7 CPU variant : 0x0 CPU part : 0xc07 CPU revision : 3 processor : 4 model name : ARMv7 Processor rev 3 (v7l) BogoMIPS : 114.00 Features : swp half thumb fastmult vfp edsp neon vfpv3 tls vfpv4 idiva idivt CPU implementer : 0x41 CPU architecture: 7 CPU variant : 0x2 CPU part : 0xc0f CPU revision : 3 processor : 5 model name : ARMv7 Processor rev 3 (v7l) BogoMIPS : 114.00 Features : swp half thumb fastmult vfp edsp neon vfpv3 tls vfpv4 idiva idivt CPU implementer : 0x41 CPU architecture: 7 CPU variant : 0x2 CPU part : 0xc0f CPU revision : 3 processor : 6 model name : ARMv7 Processor rev 3 (v7l) BogoMIPS : 114.00 Features : swp half thumb fastmult vfp edsp neon vfpv3 tls vfpv4 idiva idivt CPU implementer : 0x41 CPU architecture: 7 CPU variant : 0x2 CPU part : 0xc0f CPU revision : 3 processor : 7 model name : ARMv7 Processor rev 3 (v7l) BogoMIPS : 114.00 Features : swp half thumb fastmult vfp edsp neon vfpv3 tls vfpv4 idiva idivt CPU implementer : 0x41 CPU architecture: 7 CPU variant : 0x2 CPU part : 0xc0f CPU revision : 3 Hardware : ODROID-XU3 Revision : 0000 Serial : 0000000000000000
big core (A15):
tinymembench v0.4.9 (simple benchmark for memory throughput and latency)
==========================================================================
== Memory bandwidth tests ==
== ==
== Note 1: 1MB = 1000000 bytes ==
== Note 2: Results for 'copy' tests show how many bytes can be ==
== copied per second (adding together read and writen ==
== bytes would have provided twice higher numbers) ==
== Note 3: 2-pass copy means that we are using a small temporary buffer ==
== to first fetch data into it, and only then write it to the ==
== destination (source -> L1 cache, L1 cache -> destination) ==
== Note 4: If sample standard deviation exceeds 0.1%, it is shown in ==
== brackets ==
==========================================================================
C copy backwards : 1170.9 MB/s (0.3%)
C copy backwards (32 byte blocks) : 1167.8 MB/s
C copy backwards (64 byte blocks) : 2336.2 MB/s
C copy : 2509.9 MB/s
C copy prefetched (32 bytes step) : 2815.9 MB/s
C copy prefetched (64 bytes step) : 2836.0 MB/s
C 2-pass copy : 1374.0 MB/s
C 2-pass copy prefetched (32 bytes step) : 1605.6 MB/s
C 2-pass copy prefetched (64 bytes step) : 1629.8 MB/s
C fill : 4688.4 MB/s (0.3%)
C fill (shuffle within 16 byte blocks) : 1432.3 MB/s
C fill (shuffle within 32 byte blocks) : 1432.5 MB/s
C fill (shuffle within 64 byte blocks) : 1441.1 MB/s
---
standard memcpy : 2268.1 MB/s
standard memset : 4690.1 MB/s (0.3%)
---
NEON read : 3282.1 MB/s
NEON read prefetched (32 bytes step) : 4187.8 MB/s
NEON read prefetched (64 bytes step) : 4195.9 MB/s
NEON read 2 data streams : 3301.6 MB/s
NEON read 2 data streams prefetched (32 bytes step) : 4230.1 MB/s
NEON read 2 data streams prefetched (64 bytes step) : 4234.6 MB/s
NEON copy : 2561.6 MB/s
NEON copy prefetched (32 bytes step) : 2851.7 MB/s
NEON copy prefetched (64 bytes step) : 2847.8 MB/s
NEON unrolled copy : 2240.7 MB/s
NEON unrolled copy prefetched (32 bytes step) : 3147.9 MB/s
NEON unrolled copy prefetched (64 bytes step) : 3170.0 MB/s
NEON copy backwards : 1182.4 MB/s
NEON copy backwards prefetched (32 bytes step) : 1223.0 MB/s
NEON copy backwards prefetched (64 bytes step) : 1222.4 MB/s
NEON 2-pass copy : 1993.3 MB/s
NEON 2-pass copy prefetched (32 bytes step) : 2216.6 MB/s
NEON 2-pass copy prefetched (64 bytes step) : 2223.4 MB/s
NEON unrolled 2-pass copy : 1378.3 MB/s
NEON unrolled 2-pass copy prefetched (32 bytes step) : 1682.0 MB/s
NEON unrolled 2-pass copy prefetched (64 bytes step) : 1702.0 MB/s
NEON fill : 4687.3 MB/s (0.3%)
NEON fill backwards : 1432.4 MB/s
VFP copy : 2444.2 MB/s
VFP 2-pass copy : 1304.2 MB/s
ARM fill (STRD) : 4689.4 MB/s (0.2%)
ARM fill (STM with 8 registers) : 4691.2 MB/s
ARM fill (STM with 4 registers) : 4695.0 MB/s
ARM copy prefetched (incr pld) : 2864.5 MB/s
ARM copy prefetched (wrap pld) : 2715.5 MB/s
ARM 2-pass copy prefetched (incr pld) : 1606.0 MB/s
ARM 2-pass copy prefetched (wrap pld) : 1601.9 MB/s
==========================================================================
== Memory latency test ==
== ==
== Average time is measured for random memory accesses in the buffers ==
== of different sizes. The larger is the buffer, the more significant ==
== are relative contributions of TLB, L1/L2 cache misses and SDRAM ==
== accesses. For extremely large buffer sizes we are expecting to see ==
== page table walk with several requests to SDRAM for almost every ==
== memory access (though 64MiB is not nearly large enough to experience ==
== this effect to its fullest). ==
== ==
== Note 1: All the numbers are representing extra time, which needs to ==
== be added to L1 cache latency. The cycle timings for L1 cache ==
== latency can be usually found in the processor documentation. ==
== Note 2: Dual random read means that we are simultaneously performing ==
== two independent memory accesses at a time. In the case if ==
== the memory subsystem can't handle multiple outstanding ==
== requests, dual random read has the same timings as two ==
== single reads performed one after another. ==
==========================================================================
block size : single random read / dual random read
1024 : 0.0 ns / 0.0 ns
2048 : 0.0 ns / 0.0 ns
4096 : 0.0 ns / 0.0 ns
8192 : 0.0 ns / 0.0 ns
16384 : 0.0 ns / 0.0 ns
32768 : 0.0 ns / 0.0 ns
65536 : 4.7 ns / 7.1 ns
131072 : 7.1 ns / 9.4 ns
262144 : 10.1 ns / 12.5 ns
524288 : 11.6 ns / 14.3 ns
1048576 : 12.6 ns / 15.2 ns
2097152 : 21.5 ns / 29.9 ns
4194304 : 97.3 ns / 147.1 ns
8388608 : 137.2 ns / 187.9 ns
16777216 : 158.1 ns / 205.6 ns
33554432 : 174.0 ns / 223.7 ns
67108864 : 183.6 ns / 236.8 ns
little core (A7)
tinymembench v0.4.9 (simple benchmark for memory throughput and latency)
==========================================================================
== Memory bandwidth tests ==
== ==
== Note 1: 1MB = 1000000 bytes ==
== Note 2: Results for 'copy' tests show how many bytes can be ==
== copied per second (adding together read and writen ==
== bytes would have provided twice higher numbers) ==
== Note 3: 2-pass copy means that we are using a small temporary buffer ==
== to first fetch data into it, and only then write it to the ==
== destination (source -> L1 cache, L1 cache -> destination) ==
== Note 4: If sample standard deviation exceeds 0.1%, it is shown in ==
== brackets ==
==========================================================================
C copy backwards : 223.7 MB/s
C copy backwards (32 byte blocks) : 268.7 MB/s
C copy backwards (64 byte blocks) : 282.1 MB/s
C copy : 283.2 MB/s
C copy prefetched (32 bytes step) : 569.9 MB/s
C copy prefetched (64 bytes step) : 711.6 MB/s
C 2-pass copy : 281.0 MB/s
C 2-pass copy prefetched (32 bytes step) : 401.1 MB/s
C 2-pass copy prefetched (64 bytes step) : 425.2 MB/s
C fill : 798.7 MB/s
C fill (shuffle within 16 byte blocks) : 821.6 MB/s
C fill (shuffle within 32 byte blocks) : 452.8 MB/s
C fill (shuffle within 64 byte blocks) : 453.2 MB/s
---
standard memcpy : 298.0 MB/s
standard memset : 775.2 MB/s
---
NEON read : 464.9 MB/s
NEON read prefetched (32 bytes step) : 914.4 MB/s
NEON read prefetched (64 bytes step) : 963.1 MB/s
NEON read 2 data streams : 475.2 MB/s
NEON read 2 data streams prefetched (32 bytes step) : 957.2 MB/s
NEON read 2 data streams prefetched (64 bytes step) : 1007.6 MB/s
NEON copy : 288.1 MB/s
NEON copy prefetched (32 bytes step) : 690.9 MB/s
NEON copy prefetched (64 bytes step) : 710.3 MB/s
NEON unrolled copy : 274.0 MB/s
NEON unrolled copy prefetched (32 bytes step) : 442.8 MB/s
NEON unrolled copy prefetched (64 bytes step) : 647.4 MB/s
NEON copy backwards : 275.4 MB/s
NEON copy backwards prefetched (32 bytes step) : 682.9 MB/s
NEON copy backwards prefetched (64 bytes step) : 705.6 MB/s
NEON 2-pass copy : 285.5 MB/s
NEON 2-pass copy prefetched (32 bytes step) : 409.5 MB/s
NEON 2-pass copy prefetched (64 bytes step) : 426.2 MB/s
NEON unrolled 2-pass copy : 267.1 MB/s
NEON unrolled 2-pass copy prefetched (32 bytes step) : 367.1 MB/s
NEON unrolled 2-pass copy prefetched (64 bytes step) : 404.3 MB/s
NEON fill : 821.9 MB/s
NEON fill backwards : 821.8 MB/s
VFP copy : 275.4 MB/s
VFP 2-pass copy : 271.9 MB/s
ARM fill (STRD) : 775.6 MB/s
ARM fill (STM with 8 registers) : 821.6 MB/s
ARM fill (STM with 4 registers) : 798.4 MB/s
ARM copy prefetched (incr pld) : 669.2 MB/s
ARM copy prefetched (wrap pld) : 653.9 MB/s
ARM 2-pass copy prefetched (incr pld) : 404.7 MB/s
ARM 2-pass copy prefetched (wrap pld) : 398.1 MB/s
==========================================================================
== Memory latency test ==
== ==
== Average time is measured for random memory accesses in the buffers ==
== of different sizes. The larger is the buffer, the more significant ==
== are relative contributions of TLB, L1/L2 cache misses and SDRAM ==
== accesses. For extremely large buffer sizes we are expecting to see ==
== page table walk with several requests to SDRAM for almost every ==
== memory access (though 64MiB is not nearly large enough to experience ==
== this effect to its fullest). ==
== ==
== Note 1: All the numbers are representing extra time, which needs to ==
== be added to L1 cache latency. The cycle timings for L1 cache ==
== latency can be usually found in the processor documentation. ==
== Note 2: Dual random read means that we are simultaneously performing ==
== two independent memory accesses at a time. In the case if ==
== the memory subsystem can't handle multiple outstanding ==
== requests, dual random read has the same timings as two ==
== single reads performed one after another. ==
==========================================================================
block size : single random read / dual random read
1024 : 0.0 ns / 0.0 ns
2048 : 0.0 ns / 0.0 ns
4096 : 0.0 ns / 0.0 ns
8192 : 0.0 ns / 0.0 ns
16384 : 0.0 ns / 0.0 ns
32768 : 0.0 ns / 0.0 ns
65536 : 4.5 ns / 8.1 ns
131072 : 6.9 ns / 11.7 ns
262144 : 8.2 ns / 13.3 ns
524288 : 12.2 ns / 19.1 ns
1048576 : 77.4 ns / 120.1 ns
2097152 : 115.6 ns / 158.7 ns
4194304 : 135.5 ns / 173.7 ns
8388608 : 147.1 ns / 181.2 ns
16777216 : 155.5 ns / 188.1 ns
33554432 : 164.3 ns / 200.2 ns
67108864 : 178.2 ns / 225.0 ns