processor : 0
model name : ARMv7 Processor rev 1 (v7l)
BogoMIPS : 1600.00
Features : half thumb fastmult vfp edsp neon vfpv3 tls vfpd32
CPU implementer : 0x41
CPU architecture: 7
CPU variant : 0x4
CPU part : 0xc09
CPU revision : 1
processor : 1
model name : ARMv7 Processor rev 1 (v7l)
BogoMIPS : 1600.00
Features : half thumb fastmult vfp edsp neon vfpv3 tls vfpd32
CPU implementer : 0x41
CPU architecture: 7
CPU variant : 0x4
CPU part : 0xc09
CPU revision : 1
Hardware : Marvell Armada 380/385 (Device Tree)
Revision : 0000
Serial : 0000000000000000
tinymembench v0.4.9 (simple benchmark for memory throughput and latency)
==========================================================================
== Memory bandwidth tests ==
== ==
== Note 1: 1MB = 1000000 bytes ==
== Note 2: Results for 'copy' tests show how many bytes can be ==
== copied per second (adding together read and writen ==
== bytes would have provided twice higher numbers) ==
== Note 3: 2-pass copy means that we are using a small temporary buffer ==
== to first fetch data into it, and only then write it to the ==
== destination (source -> L1 cache, L1 cache -> destination) ==
== Note 4: If sample standard deviation exceeds 0.1%, it is shown in ==
== brackets ==
==========================================================================
C copy backwards : 719.5 MB/s (0.5%)
C copy backwards (32 byte blocks) : 771.7 MB/s (3.5%)
C copy backwards (64 byte blocks) : 638.5 MB/s (2.0%)
C copy : 814.5 MB/s (0.9%)
C copy prefetched (32 bytes step) : 885.3 MB/s (0.3%)
C copy prefetched (64 bytes step) : 896.5 MB/s (4.1%)
C 2-pass copy : 746.7 MB/s (0.2%)
C 2-pass copy prefetched (32 bytes step) : 838.0 MB/s
C 2-pass copy prefetched (64 bytes step) : 957.1 MB/s (3.5%)
C fill : 4724.7 MB/s (0.2%)
C fill (shuffle within 16 byte blocks) : 4706.4 MB/s (9.8%)
C fill (shuffle within 32 byte blocks) : 4760.4 MB/s (5.1%)
C fill (shuffle within 64 byte blocks) : 1026.9 MB/s
---
standard memcpy : 936.7 MB/s (1.0%)
standard memset : 4759.1 MB/s (8.1%)
---
NEON read : 1102.0 MB/s (0.9%)
NEON read prefetched (32 bytes step) : 1516.7 MB/s (0.7%)
NEON read prefetched (64 bytes step) : 1826.1 MB/s (2.3%)
NEON read 2 data streams : 1466.1 MB/s (1.5%)
NEON read 2 data streams prefetched (32 bytes step) : 1477.9 MB/s (2.6%)
NEON read 2 data streams prefetched (64 bytes step) : 1579.6 MB/s
NEON copy : 820.2 MB/s (2.3%)
NEON copy prefetched (32 bytes step) : 896.5 MB/s (4.1%)
NEON copy prefetched (64 bytes step) : 1080.7 MB/s
NEON unrolled copy : 825.0 MB/s (2.6%)
NEON unrolled copy prefetched (32 bytes step) : 894.7 MB/s (0.6%)
NEON unrolled copy prefetched (64 bytes step) : 978.0 MB/s (2.8%)
NEON copy backwards : 812.3 MB/s (0.2%)
NEON copy backwards prefetched (32 bytes step) : 971.5 MB/s (3.8%)
NEON copy backwards prefetched (64 bytes step) : 1034.0 MB/s (3.9%)
NEON 2-pass copy : 718.9 MB/s (2.1%)
NEON 2-pass copy prefetched (32 bytes step) : 849.6 MB/s (0.4%)
NEON 2-pass copy prefetched (64 bytes step) : 895.4 MB/s (3.6%)
NEON unrolled 2-pass copy : 702.1 MB/s
NEON unrolled 2-pass copy prefetched (32 bytes step) : 893.0 MB/s (1.7%)
NEON unrolled 2-pass copy prefetched (64 bytes step) : 1010.3 MB/s (0.8%)
NEON fill : 4204.2 MB/s
NEON fill backwards : 4179.5 MB/s (2.5%)
VFP copy : 858.2 MB/s (0.8%)
VFP 2-pass copy : 824.8 MB/s (4.3%)
ARM fill (STRD) : 4746.0 MB/s (8.1%)
ARM fill (STM with 8 registers) : 4734.2 MB/s (1.5%)
ARM fill (STM with 4 registers) : 4763.6 MB/s (10.7%)
ARM copy prefetched (incr pld) : 882.5 MB/s (3.0%)
ARM copy prefetched (wrap pld) : 882.9 MB/s (0.7%)
ARM 2-pass copy prefetched (incr pld) : 965.3 MB/s (0.6%)
ARM 2-pass copy prefetched (wrap pld) : 966.7 MB/s (0.2%)
==========================================================================
== Memory latency test ==
== ==
== Average time is measured for random memory accesses in the buffers ==
== of different sizes. The larger is the buffer, the more significant ==
== are relative contributions of TLB, L1/L2 cache misses and SDRAM ==
== accesses. For extremely large buffer sizes we are expecting to see ==
== page table walk with several requests to SDRAM for almost every ==
== memory access (though 64MiB is not nearly large enough to experience ==
== this effect to its fullest). ==
== ==
== Note 1: All the numbers are representing extra time, which needs to ==
== be added to L1 cache latency. The cycle timings for L1 cache ==
== latency can be usually found in the processor documentation. ==
== Note 2: Dual random read means that we are simultaneously performing ==
== two independent memory accesses at a time. In the case if ==
== the memory subsystem can't handle multiple outstanding ==
== requests, dual random read has the same timings as two ==
== single reads performed one after another. ==
==========================================================================
block size : single random read / dual random read
1024 : 0.0 ns / 0.0 ns
2048 : 0.0 ns / 0.0 ns
4096 : 0.0 ns / 0.0 ns
8192 : 0.0 ns / 0.0 ns
16384 : 0.0 ns / 0.0 ns
32768 : 0.0 ns / 0.5 ns
65536 : 9.2 ns / 14.0 ns
131072 : 13.4 ns / 17.2 ns
262144 : 17.5 ns / 21.7 ns
524288 : 20.0 ns / 24.2 ns
1048576 : 24.9 ns / 31.0 ns
2097152 : 58.1 ns / 85.3 ns
4194304 : 80.4 ns / 113.2 ns
8388608 : 92.4 ns / 128.9 ns
16777216 : 100.7 ns / 139.0 ns
33554432 : 109.1 ns / 149.8 ns
67108864 : 115.9 ns / 160.7 ns