Intel Core 2 Quad Q9400 - ssvb/tinymembench GitHub Wiki
Intel Core 2 Quad Q9400, 4x2GB DDR3-1066
$ lscpu
Architecture: x86_64
CPU op-mode(s): 32-bit, 64-bit
Byte Order: Little Endian
CPU(s): 4
On-line CPU(s) list: 0-3
Thread(s) per core: 1
Core(s) per socket: 4
Socket(s): 1
NUMA node(s): 1
Vendor ID: GenuineIntel
CPU family: 6
Model: 23
Model name: Intel(R) Core(TM)2 Quad CPU Q9400 @ 2.66GHz
Stepping: 10
CPU MHz: 1994.856
CPU max MHz: 2667.0000
CPU min MHz: 2000.0000
BogoMIPS: 5319.62
Virtualization: VT-x
L1d cache: 32K
L1i cache: 32K
L2 cache: 3072K
NUMA node0 CPU(s): 0-3
Flags: fpu vme de pse tsc msr pae mce cx8 apic sep mtrr pge mca cmov pat pse36 clflush dts acpi mmx fxsr sse sse2 ss ht tm pbe syscall nx lm constant_tsc arch_perfmon pebs bts rep_good nopl cpuid aperfmperf pni dtes64 monitor ds_cpl vmx smx est tm2 ssse3 cx16 xtpr pdcm sse4_1 xsave lahf_lm pti tpr_shadow vnmi flexpriority dtherm
tinymembench v0.4.9 (simple benchmark for memory throughput and latency)
==========================================================================
== Memory bandwidth tests ==
== ==
== Note 1: 1MB = 1000000 bytes ==
== Note 2: Results for 'copy' tests show how many bytes can be ==
== copied per second (adding together read and writen ==
== bytes would have provided twice higher numbers) ==
== Note 3: 2-pass copy means that we are using a small temporary buffer ==
== to first fetch data into it, and only then write it to the ==
== destination (source -> L1 cache, L1 cache -> destination) ==
== Note 4: If sample standard deviation exceeds 0.1%, it is shown in ==
== brackets ==
==========================================================================
C copy backwards : 1915.7 MB/s (0.7%)
C copy backwards (32 byte blocks) : 1926.1 MB/s (1.1%)
C copy backwards (64 byte blocks) : 1925.3 MB/s (0.9%)
C copy : 1924.6 MB/s (0.8%)
C copy prefetched (32 bytes step) : 1921.8 MB/s (0.8%)
C copy prefetched (64 bytes step) : 1921.6 MB/s (0.8%)
C 2-pass copy : 1858.5 MB/s (0.8%)
C 2-pass copy prefetched (32 bytes step) : 1899.9 MB/s (0.6%)
C 2-pass copy prefetched (64 bytes step) : 1907.9 MB/s (0.7%)
C fill : 2257.7 MB/s (0.8%)
C fill (shuffle within 16 byte blocks) : 2259.0 MB/s (0.7%)
C fill (shuffle within 32 byte blocks) : 2253.8 MB/s (0.8%)
C fill (shuffle within 64 byte blocks) : 2255.7 MB/s (0.9%)
---
standard memcpy : 3523.6 MB/s (1.0%)
standard memset : 2247.6 MB/s (1.2%)
---
MOVSB copy : 2059.4 MB/s (0.7%)
MOVSD copy : 2053.8 MB/s (8.5%)
SSE2 copy : 1942.4 MB/s (2.6%)
SSE2 nontemporal copy : 3447.7 MB/s (1.2%)
SSE2 copy prefetched (32 bytes step) : 1908.9 MB/s (0.8%)
SSE2 copy prefetched (64 bytes step) : 1907.0 MB/s (0.8%)
SSE2 nontemporal copy prefetched (32 bytes step) : 3481.8 MB/s (1.2%)
SSE2 nontemporal copy prefetched (64 bytes step) : 3499.5 MB/s (1.3%)
SSE2 2-pass copy : 1886.0 MB/s (1.2%)
SSE2 2-pass copy prefetched (32 bytes step) : 1891.4 MB/s (1.1%)
SSE2 2-pass copy prefetched (64 bytes step) : 1897.0 MB/s (1.3%)
SSE2 2-pass nontemporal copy : 1633.9 MB/s (1.7%)
SSE2 fill : 2249.6 MB/s (1.0%)
SSE2 nontemporal fill : 6860.5 MB/s (1.6%)
==========================================================================
== Memory latency test ==
== ==
== Average time is measured for random memory accesses in the buffers ==
== of different sizes. The larger is the buffer, the more significant ==
== are relative contributions of TLB, L1/L2 cache misses and SDRAM ==
== accesses. For extremely large buffer sizes we are expecting to see ==
== page table walk with several requests to SDRAM for almost every ==
== memory access (though 64MiB is not nearly large enough to experience ==
== this effect to its fullest). ==
== ==
== Note 1: All the numbers are representing extra time, which needs to ==
== be added to L1 cache latency. The cycle timings for L1 cache ==
== latency can be usually found in the processor documentation. ==
== Note 2: Dual random read means that we are simultaneously performing ==
== two independent memory accesses at a time. In the case if ==
== the memory subsystem can't handle multiple outstanding ==
== requests, dual random read has the same timings as two ==
== single reads performed one after another. ==
==========================================================================
block size : single random read / dual random read, [MADV_NOHUGEPAGE]
1024 : 0.0 ns / 0.0 ns
2048 : 0.0 ns / 0.0 ns
4096 : 0.0 ns / 0.0 ns
8192 : 0.0 ns / 0.0 ns
16384 : 0.0 ns / 0.0 ns
32768 : 0.0 ns / 0.0 ns
65536 : 2.6 ns / 4.3 ns
131072 : 4.3 ns / 6.7 ns
262144 : 5.2 ns / 7.8 ns
524288 : 5.6 ns / 8.2 ns
1048576 : 5.8 ns / 8.6 ns
2097152 : 7.5 ns / 9.3 ns
4194304 : 29.4 ns / 47.7 ns
8388608 : 59.5 ns / 86.9 ns
16777216 : 75.6 ns / 102.2 ns
33554432 : 84.3 ns / 108.4 ns
67108864 : 88.5 ns / 111.9 ns
block size : single random read / dual random read, [MADV_HUGEPAGE]
1024 : 0.0 ns / 0.0 ns
2048 : 0.0 ns / 0.0 ns
4096 : 0.0 ns / 0.0 ns
8192 : 0.0 ns / 0.0 ns
16384 : 0.0 ns / 0.0 ns
32768 : 0.0 ns / 0.0 ns
65536 : 2.6 ns / 4.2 ns
131072 : 3.9 ns / 5.6 ns
262144 : 4.6 ns / 6.1 ns
524288 : 4.9 ns / 6.4 ns
1048576 : 5.1 ns / 6.5 ns
2097152 : 5.3 ns / 6.6 ns
4194304 : 25.8 ns / 42.3 ns
8388608 : 55.4 ns / 78.2 ns
16777216 : 70.0 ns / 89.4 ns
33554432 : 77.5 ns / 93.9 ns
67108864 : 81.2 ns / 96.5 ns