Intel(R) Core(TM) i9‐13900K - ssvb/tinymembench GitHub Wiki
tinymembench v0.4.9 (simple benchmark for memory throughput and latency)
==========================================================================
== Memory bandwidth tests ==
== ==
== Note 1: 1MB = 1000000 bytes ==
== Note 2: Results for 'copy' tests show how many bytes can be ==
== copied per second (adding together read and writen ==
== bytes would have provided twice higher numbers) ==
== Note 3: 2-pass copy means that we are using a small temporary buffer ==
== to first fetch data into it, and only then write it to the ==
== destination (source -> L1 cache, L1 cache -> destination) ==
== Note 4: If sample standard deviation exceeds 0.1%, it is shown in ==
== brackets ==
==========================================================================
C copy backwards : 16178.2 MB/s (0.3%)
C copy backwards (32 byte blocks) : 16148.8 MB/s (0.2%)
C copy backwards (64 byte blocks) : 16162.6 MB/s
C copy : 15891.5 MB/s
C copy prefetched (32 bytes step) : 15767.3 MB/s
C copy prefetched (64 bytes step) : 15813.5 MB/s (0.2%)
C 2-pass copy : 12924.6 MB/s (0.3%)
C 2-pass copy prefetched (32 bytes step) : 12329.5 MB/s (0.1%)
C 2-pass copy prefetched (64 bytes step) : 12502.7 MB/s
C fill : 43526.2 MB/s
C fill (shuffle within 16 byte blocks) : 43536.9 MB/s (0.2%)
C fill (shuffle within 32 byte blocks) : 43598.9 MB/s (0.2%)
C fill (shuffle within 64 byte blocks) : 43551.0 MB/s (0.2%)
---
standard memcpy : 36206.3 MB/s (0.3%)
standard memset : 46670.9 MB/s
---
MOVSB copy : 19447.8 MB/s (0.2%)
MOVSD copy : 19455.4 MB/s (0.1%)
SSE2 copy : 18489.0 MB/s (0.2%)
SSE2 nontemporal copy : 29961.8 MB/s (0.2%)
SSE2 copy prefetched (32 bytes step) : 17724.2 MB/s
SSE2 copy prefetched (64 bytes step) : 17812.8 MB/s
SSE2 nontemporal copy prefetched (32 bytes step) : 25043.6 MB/s (0.2%)
SSE2 nontemporal copy prefetched (64 bytes step) : 25871.9 MB/s (0.2%)
SSE2 2-pass copy : 14424.5 MB/s
SSE2 2-pass copy prefetched (32 bytes step) : 14017.9 MB/s (0.4%)
SSE2 2-pass copy prefetched (64 bytes step) : 13952.4 MB/s (0.4%)
SSE2 2-pass nontemporal copy : 6974.2 MB/s (0.2%)
SSE2 fill : 46370.4 MB/s
SSE2 nontemporal fill : 61137.7 MB/s (0.5%)
==========================================================================
== Framebuffer read tests. ==
== ==
== Many ARM devices use a part of the system memory as the framebuffer, ==
== typically mapped as uncached but with write-combining enabled. ==
== Writes to such framebuffers are quite fast, but reads are much ==
== slower and very sensitive to the alignment and the selection of ==
== CPU instructions which are used for accessing memory. ==
== ==
== Many x86 systems allocate the framebuffer in the GPU memory, ==
== accessible for the CPU via a relatively slow PCI-E bus. Moreover, ==
== PCI-E is asymmetric and handles reads a lot worse than writes. ==
== ==
== If uncached framebuffer reads are reasonably fast (at least 100 MB/s ==
== or preferably >300 MB/s), then using the shadow framebuffer layer ==
== is not necessary in Xorg DDX drivers, resulting in a nice overall ==
== performance improvement. For example, the xf86-video-fbturbo DDX ==
== uses this trick. ==
==========================================================================
MOVSD copy (from framebuffer) : 265.6 MB/s (34.2%)
MOVSD 2-pass copy (from framebuffer) : 267.3 MB/s
SSE2 copy (from framebuffer) : 71.8 MB/s (36.0%)
SSE2 2-pass copy (from framebuffer) : 71.7 MB/s (35.2%)
==========================================================================
== Memory latency test ==
== ==
== Average time is measured for random memory accesses in the buffers ==
== of different sizes. The larger is the buffer, the more significant ==
== are relative contributions of TLB, L1/L2 cache misses and SDRAM ==
== accesses. For extremely large buffer sizes we are expecting to see ==
== page table walk with several requests to SDRAM for almost every ==
== memory access (though 64MiB is not nearly large enough to experience ==
== this effect to its fullest). ==
== ==
== Note 1: All the numbers are representing extra time, which needs to ==
== be added to L1 cache latency. The cycle timings for L1 cache ==
== latency can be usually found in the processor documentation. ==
== Note 2: Dual random read means that we are simultaneously performing ==
== two independent memory accesses at a time. In the case if ==
== the memory subsystem can't handle multiple outstanding ==
== requests, dual random read has the same timings as two ==
== single reads performed one after another. ==
==========================================================================
block size : single random read / dual random read, [MADV_NOHUGEPAGE]
1024 : 0.0 ns / 0.0 ns
2048 : 0.0 ns / 0.0 ns
4096 : 0.0 ns / 0.0 ns
8192 : 0.0 ns / 0.0 ns
16384 : 0.0 ns / 0.0 ns
32768 : 0.0 ns / 0.0 ns
65536 : 0.5 ns / 0.8 ns
131072 : 1.2 ns / 1.6 ns
262144 : 1.6 ns / 1.8 ns
524288 : 2.0 ns / 2.3 ns
1048576 : 2.6 ns / 2.9 ns
2097152 : 3.7 ns / 4.2 ns
4194304 : 7.4 ns / 9.7 ns
8388608 : 10.2 ns / 11.9 ns
16777216 : 12.5 ns / 14.6 ns
33554432 : 20.0 ns / 26.0 ns
67108864 : 45.8 ns / 64.2 ns
block size : single random read / dual random read, [MADV_HUGEPAGE]
1024 : 0.0 ns / 0.0 ns
2048 : 0.0 ns / 0.0 ns
4096 : 0.0 ns / 0.0 ns
8192 : 0.0 ns / 0.0 ns
16384 : 0.0 ns / 0.0 ns
32768 : 0.0 ns / 0.0 ns
65536 : 0.5 ns / 0.8 ns
131072 : 1.2 ns / 1.6 ns
262144 : 1.6 ns / 1.8 ns
524288 : 1.7 ns / 1.9 ns
1048576 : 1.8 ns / 1.9 ns
2097152 : 1.9 ns / 1.9 ns
4194304 : 6.2 ns / 8.6 ns
8388608 : 8.5 ns / 10.5 ns
16777216 : 9.6 ns / 11.2 ns
33554432 : 12.2 ns / 14.8 ns
67108864 : 41.1 ns / 59.4 ns