IFC6410 - ssvb/tinymembench GitHub Wiki
CPU clock speed: 1667MHz
Processor : ARMv7 Processor rev 0 (v7l)
processor : 0
BogoMIPS : 13.53
processor : 1
BogoMIPS : 13.53
processor : 2
BogoMIPS : 13.53
processor : 3
BogoMIPS : 13.53
Features : swp half thumb fastmult vfp edsp neon vfpv3 tls vfpv4
CPU implementer : 0x51
CPU architecture: 7
CPU variant : 0x1
CPU part : 0x06f
CPU revision : 0
Hardware : QCT APQ8064 CDP
Revision : 0000
Serial : 0000000000000000
tinymembench v0.3.9 (simple benchmark for memory throughput and latency)
==========================================================================
== Memory bandwidth tests ==
== ==
== Note 1: 1MB = 1000000 bytes ==
== Note 2: Results for 'copy' tests show how many bytes can be ==
== copied per second (adding together read and writen ==
== bytes would have provided twice higher numbers) ==
== Note 3: 2-pass copy means that we are using a small temporary buffer ==
== to first fetch data into it, and only then write it to the ==
== destination (source -> L1 cache, L1 cache -> destination) ==
== Note 4: If sample standard deviation exceeds 0.1%, it is shown in ==
== brackets ==
==========================================================================
C copy backwards : 2233.9 MB/s
C copy : 1972.0 MB/s
C copy prefetched (32 bytes step) : 2551.2 MB/s (0.2%)
C copy prefetched (64 bytes step) : 2541.3 MB/s
C 2-pass copy : 1445.5 MB/s
C 2-pass copy prefetched (32 bytes step) : 1929.7 MB/s
C 2-pass copy prefetched (64 bytes step) : 1929.4 MB/s
C fill : 7622.4 MB/s
---
standard memcpy : 1610.0 MB/s
standard memset : 5978.1 MB/s
---
NEON read : 1704.8 MB/s (0.2%)
NEON read prefetched (32 bytes step) : 4234.6 MB/s (0.2%)
NEON read prefetched (64 bytes step) : 4231.3 MB/s (0.2%)
NEON read 2 data streams : 1585.6 MB/s
NEON read 2 data streams prefetched (32 bytes step) : 4840.0 MB/s (0.1%)
NEON read 2 data streams prefetched (64 bytes step) : 4879.2 MB/s
NEON copy : 1530.1 MB/s (0.1%)
NEON copy prefetched (32 bytes step) : 2513.9 MB/s (0.1%)
NEON copy prefetched (64 bytes step) : 2515.5 MB/s (0.1%)
NEON unrolled copy : 1545.5 MB/s (0.1%)
NEON unrolled copy prefetched (32 bytes step) : 3361.8 MB/s
NEON unrolled copy prefetched (64 bytes step) : 3371.1 MB/s
NEON copy backwards : 1509.9 MB/s (0.2%)
NEON copy backwards prefetched (32 bytes step) : 2966.7 MB/s
NEON copy backwards prefetched (64 bytes step) : 2983.0 MB/s (0.2%)
NEON 2-pass copy : 1345.3 MB/s (0.2%)
NEON 2-pass copy prefetched (32 bytes step) : 2206.5 MB/s
NEON 2-pass copy prefetched (64 bytes step) : 2294.2 MB/s
NEON unrolled 2-pass copy : 1301.3 MB/s
NEON unrolled 2-pass copy prefetched (32 bytes step) : 2679.9 MB/s (0.2%)
NEON unrolled 2-pass copy prefetched (64 bytes step) : 2658.7 MB/s
NEON fill : 7625.7 MB/s
NEON fill backwards : 7598.1 MB/s
VFP copy : 1544.8 MB/s
VFP 2-pass copy : 1454.1 MB/s
ARM fill (STRD) : 5984.2 MB/s
ARM fill (STM with 8 registers) : 7620.7 MB/s
ARM fill (STM with 4 registers) : 7622.8 MB/s (0.3%)
ARM copy prefetched (incr pld) : 2202.4 MB/s
ARM copy prefetched (wrap pld) : 2048.0 MB/s (0.1%)
ARM 2-pass copy prefetched (incr pld) : 1823.2 MB/s (0.2%)
ARM 2-pass copy prefetched (wrap pld) : 1713.5 MB/s
==========================================================================
== Memory latency test ==
== ==
== Average time is measured for random memory accesses in the buffers ==
== of different sizes. The larger is the buffer, the more significant ==
== are relative contributions of TLB, L1/L2 cache misses and SDRAM ==
== accesses. For extremely large buffer sizes we are expecting to see ==
== page table walk with several requests to SDRAM for almost every ==
== memory access (though 64MiB is not nearly large enough to experience ==
== this effect to its fullest). ==
== ==
== Note 1: All the numbers are representing extra time, which needs to ==
== be added to L1 cache latency. The cycle timings for L1 cache ==
== latency can be usually found in the processor documentation. ==
== Note 2: Dual random read means that we are simultaneously performing ==
== two independent memory accesses at a time. In the case if ==
== the memory subsystem can't handle multiple outstanding ==
== requests, dual random read has the same timings as two ==
== single reads performed one after another. ==
==========================================================================
block size : single random read / dual random read
1024 : 0.0 ns / 0.0 ns
2048 : 0.0 ns / 0.0 ns
4096 : 0.0 ns / 0.0 ns
8192 : 0.9 ns / 1.1 ns
16384 : 1.4 ns / 1.5 ns
32768 : 12.4 ns / 17.4 ns
65536 : 17.3 ns / 21.4 ns
131072 : 19.6 ns / 22.6 ns
262144 : 22.8 ns / 26.0 ns
524288 : 24.5 ns / 27.4 ns
1048576 : 45.2 ns / 68.4 ns
2097152 : 73.6 ns / 119.6 ns
4194304 : 144.8 ns / 191.0 ns
8388608 : 161.7 ns / 206.9 ns
16777216 : 175.0 ns / 218.9 ns
33554432 : 182.7 ns / 226.4 ns
67108864 : 188.7 ns / 235.3 ns