DragonBoard 810 (APQ8094) - ssvb/tinymembench GitHub Wiki
Processor : AArch64 Processor rev 2 (aarch64) processor : 0 processor : 1 processor : 2 processor : 3 processor : 4 processor : 5 processor : 6 processor : 7 Features : fp asimd evtstrm aes pmull sha1 sha2 crc32 CPU implementer : 0x41 CPU architecture: 8 CPU variant : 0x0 CPU part : 0xd03 CPU revision : 2 Hardware : Qualcomm Technologies, Inc APQ8094
Cortex-A53 - Aarch64:
tinymembench v0.3.9 (simple benchmark for memory throughput and latency)
==========================================================================
== Memory bandwidth tests ==
== ==
== Note 1: 1MB = 1000000 bytes ==
== Note 2: Results for 'copy' tests show how many bytes can be ==
== copied per second (adding together read and writen ==
== bytes would have provided twice higher numbers) ==
== Note 3: 2-pass copy means that we are using a small temporary buffer ==
== to first fetch data into it, and only then write it to the ==
== destination (source -> L1 cache, L1 cache -> destination) ==
== Note 4: If sample standard deviation exceeds 0.1%, it is shown in ==
== brackets ==
==========================================================================
C copy backwards : 2213.0 MB/s (0.5%)
C copy : 2215.1 MB/s (0.3%)
C copy prefetched (32 bytes step) : 1385.0 MB/s (0.1%)
C copy prefetched (64 bytes step) : 1385.6 MB/s (0.1%)
C 2-pass copy : 1835.7 MB/s (0.2%)
C 2-pass copy prefetched (32 bytes step) : 976.2 MB/s (0.3%)
C 2-pass copy prefetched (64 bytes step) : 976.5 MB/s (0.2%)
C fill : 12110.5 MB/s (0.6%)
---
standard memcpy : 2154.7 MB/s (0.3%)
standard memset : 12129.6 MB/s (0.8%)
==========================================================================
== Memory latency test ==
== ==
== Average time is measured for random memory accesses in the buffers ==
== of different sizes. The larger is the buffer, the more significant ==
== are relative contributions of TLB, L1/L2 cache misses and SDRAM ==
== accesses. For extremely large buffer sizes we are expecting to see ==
== page table walk with several requests to SDRAM for almost every ==
== memory access (though 64MiB is not nearly large enough to experience ==
== this effect to its fullest). ==
== ==
== Note 1: All the numbers are representing extra time, which needs to ==
== be added to L1 cache latency. The cycle timings for L1 cache ==
== latency can be usually found in the processor documentation. ==
== Note 2: Dual random read means that we are simultaneously performing ==
== two independent memory accesses at a time. In the case if ==
== the memory subsystem can't handle multiple outstanding ==
== requests, dual random read has the same timings as two ==
== single reads performed one after another. ==
==========================================================================
block size : single random read / dual random read
1024 : 0.0 ns / 0.0 ns
2048 : 0.0 ns / 0.0 ns
4096 : 0.0 ns / 0.0 ns
8192 : 0.0 ns / 0.0 ns
16384 : 0.0 ns / 0.0 ns
32768 : 0.0 ns / 0.0 ns
65536 : 4.5 ns / 7.4 ns
131072 : 6.9 ns / 10.5 ns
262144 : 8.3 ns / 11.8 ns
524288 : 15.3 ns / 20.7 ns
1048576 : 166.1 ns / 192.1 ns
2097152 : 239.2 ns / 226.7 ns
4194304 : 279.2 ns / 247.7 ns
8388608 : 301.7 ns / 256.7 ns
16777216 : 318.0 ns / 262.9 ns
33554432 : 324.6 ns / 265.9 ns
67108864 : 331.5 ns / 271.4 ns
Cortex-A57 - Aarch64:
tinymembench v0.3.9 (simple benchmark for memory throughput and latency)
==========================================================================
== Memory bandwidth tests ==
== ==
== Note 1: 1MB = 1000000 bytes ==
== Note 2: Results for 'copy' tests show how many bytes can be ==
== copied per second (adding together read and writen ==
== bytes would have provided twice higher numbers) ==
== Note 3: 2-pass copy means that we are using a small temporary buffer ==
== to first fetch data into it, and only then write it to the ==
== destination (source -> L1 cache, L1 cache -> destination) ==
== Note 4: If sample standard deviation exceeds 0.1%, it is shown in ==
== brackets ==
==========================================================================
C copy backwards : 3373.9 MB/s
C copy : 3663.6 MB/s (0.5%)
C copy prefetched (32 bytes step) : 3967.9 MB/s (0.9%)
C copy prefetched (64 bytes step) : 3966.2 MB/s (0.7%)
C 2-pass copy : 3441.1 MB/s (0.6%)
C 2-pass copy prefetched (32 bytes step) : 3678.6 MB/s (0.5%)
C 2-pass copy prefetched (64 bytes step) : 3687.7 MB/s (0.5%)
C fill : 11923.3 MB/s (0.6%)
---
standard memcpy : 3625.6 MB/s
standard memset : 11909.8 MB/s (0.5%)
==========================================================================
== Memory latency test ==
== ==
== Average time is measured for random memory accesses in the buffers ==
== of different sizes. The larger is the buffer, the more significant ==
== are relative contributions of TLB, L1/L2 cache misses and SDRAM ==
== accesses. For extremely large buffer sizes we are expecting to see ==
== page table walk with several requests to SDRAM for almost every ==
== memory access (though 64MiB is not nearly large enough to experience ==
== this effect to its fullest). ==
== ==
== Note 1: All the numbers are representing extra time, which needs to ==
== be added to L1 cache latency. The cycle timings for L1 cache ==
== latency can be usually found in the processor documentation. ==
== Note 2: Dual random read means that we are simultaneously performing ==
== two independent memory accesses at a time. In the case if ==
== the memory subsystem can't handle multiple outstanding ==
== requests, dual random read has the same timings as two ==
== single reads performed one after another. ==
==========================================================================
block size : single random read / dual random read
1024 : 0.0 ns / 0.0 ns
2048 : 0.0 ns / 0.0 ns
4096 : 0.0 ns / 0.0 ns
8192 : 0.0 ns / 0.0 ns
16384 : 0.0 ns / 0.0 ns
32768 : 0.0 ns / 0.0 ns
65536 : 5.2 ns / 8.0 ns
131072 : 7.8 ns / 10.5 ns
262144 : 11.0 ns / 13.6 ns
524288 : 12.6 ns / 15.4 ns
1048576 : 14.2 ns / 16.4 ns
2097152 : 72.6 ns / 133.6 ns
4194304 : 176.9 ns / 210.9 ns
8388608 : 262.4 ns / 259.8 ns
16777216 : 307.9 ns / 287.6 ns
33554432 : 331.6 ns / 298.1 ns
67108864 : 370.0 ns / 346.7 ns