# cat /proc/cpuinfo
processor : 0
model name : ARMv7 Processor rev 5 (v7l)
BogoMIPS : 789.70
Features : swp half thumb fastmult vfp edsp iwmmxt thumbee vfpv3 vfpv3d16 tls
CPU implementer : 0x56
CPU architecture: 7
CPU variant : 0x0
CPU part : 0x581
CPU revision : 5
Hardware : Marvell Dove (Flattened Device Tree)
Revision : 0000
Serial : 0000000000000000
tinymembench v0.4 (simple benchmark for memory throughput and latency)
==========================================================================
== Memory bandwidth tests ==
== ==
== Note 1: 1MB = 1000000 bytes ==
== Note 2: Results for 'copy' tests show how many bytes can be ==
== copied per second (adding together read and writen ==
== bytes would have provided twice higher numbers) ==
== Note 3: 2-pass copy means that we are using a small temporary buffer ==
== to first fetch data into it, and only then write it to the ==
== destination (source -> L1 cache, L1 cache -> destination) ==
== Note 4: If sample standard deviation exceeds 0.1%, it is shown in ==
== brackets ==
==========================================================================
C copy backwards : 239.3 MB/s
C copy backwards (32 byte blocks) : 296.3 MB/s
C copy backwards (64 byte blocks) : 296.3 MB/s
C copy : 296.3 MB/s
C copy prefetched (32 bytes step) : 289.0 MB/s
C copy prefetched (64 bytes step) : 313.3 MB/s
C 2-pass copy : 285.0 MB/s
C 2-pass copy prefetched (32 bytes step) : 324.9 MB/s
C 2-pass copy prefetched (64 bytes step) : 299.6 MB/s
C fill : 1536.9 MB/s
C fill (shuffle within 16 byte blocks) : 985.0 MB/s
C fill (shuffle within 32 byte blocks) : 739.3 MB/s
C fill (shuffle within 64 byte blocks) : 739.3 MB/s
---
standard memcpy : 270.5 MB/s
standard memset : 1205.6 MB/s
---
VFP copy : 233.7 MB/s
VFP 2-pass copy : 172.6 MB/s
ARM fill (STRD) : 1536.9 MB/s
ARM fill (STM with 8 registers) : 1537.0 MB/s
ARM fill (STM with 4 registers) : 1205.7 MB/s
ARM copy prefetched (incr pld) : 270.3 MB/s
ARM copy prefetched (wrap pld) : 271.3 MB/s
ARM 2-pass copy prefetched (incr pld) : 302.5 MB/s
ARM 2-pass copy prefetched (wrap pld) : 303.2 MB/s
==========================================================================
== Framebuffer read tests. ==
== ==
== Many ARM devices use a part of the system memory as the framebuffer, ==
== typically mapped as uncached but with write-combining enabled. ==
== Writes to such framebuffers are quite fast, but reads are much ==
== slower and very sensitive to the alignment and the selection of ==
== CPU instructions which are used for accessing memory. ==
== ==
== Many x86 systems allocate the framebuffer in the GPU memory, ==
== accessible for the CPU via a relatively slow PCI-E bus. Moreover, ==
== PCI-E is asymmetric and handles reads a lot worse than writes. ==
== ==
== If uncached framebuffer reads are reasonably fast (at least 100 MB/s ==
== or preferably >300 MB/s), then using the shadow framebuffer layer ==
== is not necessary in Xorg DDX drivers, resulting in a nice overall ==
== performance improvement. For example, the xf86-video-fbturbo DDX ==
== uses this trick. ==
==========================================================================
VFP copy (from framebuffer) : 58.0 MB/s
VFP 2-pass copy (from framebuffer) : 54.0 MB/s
ARM copy (from framebuffer) : 109.3 MB/s
ARM 2-pass copy (from framebuffer) : 112.1 MB/s
==========================================================================
== Memory latency test ==
== ==
== Average time is measured for random memory accesses in the buffers ==
== of different sizes. The larger is the buffer, the more significant ==
== are relative contributions of TLB, L1/L2 cache misses and SDRAM ==
== accesses. For extremely large buffer sizes we are expecting to see ==
== page table walk with several requests to SDRAM for almost every ==
== memory access (though 64MiB is not nearly large enough to experience ==
== this effect to its fullest). ==
== ==
== Note 1: All the numbers are representing extra time, which needs to ==
== be added to L1 cache latency. The cycle timings for L1 cache ==
== latency can be usually found in the processor documentation. ==
== Note 2: Dual random read means that we are simultaneously performing ==
== two independent memory accesses at a time. In the case if ==
== the memory subsystem can't handle multiple outstanding ==
== requests, dual random read has the same timings as two ==
== single reads performed one after another. ==
==========================================================================
block size : single random read / dual random read
1024 : 0.0 ns / 0.0 ns
2048 : 0.0 ns / 0.0 ns
4096 : 0.0 ns / 0.0 ns
8192 : 0.0 ns / 0.0 ns
16384 : 0.0 ns / 0.0 ns
32768 : 0.1 ns / 0.1 ns
65536 : 15.1 ns / 31.9 ns
131072 : 22.7 ns / 47.6 ns
262144 : 26.5 ns / 55.3 ns
524288 : 29.3 ns / 60.4 ns
1048576 : 96.1 ns / 193.3 ns
2097152 : 118.8 ns / 238.2 ns
4194304 : 128.6 ns / 257.6 ns
8388608 : 133.4 ns / 267.2 ns
16777216 : 138.5 ns / 277.2 ns
33554432 : 144.3 ns / 288.9 ns
67108864 : 153.9 ns / 308.0 ns