Cubietruck - ssvb/tinymembench GitHub Wiki
echo 1008000 > /sys/devices/system/cpu/cpu0/cpufreq/scaling_max_freq
echo 1 > /sys/devices/platform/disp/graphics/fb0/blank
echo 1 > /sys/devices/platform/disp/graphics/fb1/blank
# a10-meminfo
dram_clk = 528
dram_type = 3
dram_rank_num = 1
dram_chip_density = 4096
dram_io_width = 8
dram_bus_width = 32
dram_cas = 7
dram_zq = 0x7f
dram_odt_en = 0
dram_tpr0 = 0x36947790
dram_tpr1 = 0xa080
dram_tpr2 = 0x19200
dram_tpr3 = 0x72222
dram_emr1 = 0x4
dram_emr2 = 0x10
dram_emr3 = 0x0
./tinymembench
tinymembench v0.3.9 (simple benchmark for memory throughput and latency)
==========================================================================
== Memory bandwidth tests ==
== ==
== Note 1: 1MB = 1000000 bytes ==
== Note 2: Results for 'copy' tests show how many bytes can be ==
== copied per second (adding together read and writen ==
== bytes would have provided twice higher numbers) ==
== Note 3: 2-pass copy means that we are using a small temporary buffer ==
== to first fetch data into it, and only then write it to the ==
== destination (source -> L1 cache, L1 cache -> destination) ==
== Note 4: If sample standard deviation exceeds 0.1%, it is shown in ==
== brackets ==
==========================================================================
C copy backwards : 294.8 MB/s
C copy : 999.5 MB/s
C copy prefetched (32 bytes step) : 961.3 MB/s (0.4%)
C copy prefetched (64 bytes step) : 960.0 MB/s
C 2-pass copy : 787.8 MB/s (0.3%)
C 2-pass copy prefetched (32 bytes step) : 711.2 MB/s (0.3%)
C 2-pass copy prefetched (64 bytes step) : 710.9 MB/s (0.3%)
C fill : 2668.6 MB/s
---
standard memcpy : 1064.0 MB/s
standard memset : 2497.1 MB/s (0.3%)
---
NEON read : 1419.1 MB/s (0.4%)
NEON read prefetched (32 bytes step) : 1544.4 MB/s (0.3%)
NEON read prefetched (64 bytes step) : 1584.2 MB/s
NEON read 2 data streams : 406.5 MB/s (0.2%)
NEON read 2 data streams prefetched (32 bytes step) : 765.2 MB/s (0.4%)
NEON read 2 data streams prefetched (64 bytes step) : 826.6 MB/s
NEON copy : 1021.8 MB/s (0.5%)
NEON copy prefetched (32 bytes step) : 1111.5 MB/s (0.2%)
NEON copy prefetched (64 bytes step) : 1100.8 MB/s (0.2%)
NEON unrolled copy : 1077.4 MB/s (0.2%)
NEON unrolled copy prefetched (32 bytes step) : 949.1 MB/s (0.1%)
NEON unrolled copy prefetched (64 bytes step) : 1059.5 MB/s (0.6%)
NEON copy backwards : 972.6 MB/s
NEON copy backwards prefetched (32 bytes step) : 1072.4 MB/s (0.5%)
NEON copy backwards prefetched (64 bytes step) : 1074.9 MB/s (0.3%)
NEON 2-pass copy : 856.8 MB/s (0.3%)
NEON 2-pass copy prefetched (32 bytes step) : 910.0 MB/s
NEON 2-pass copy prefetched (64 bytes step) : 929.5 MB/s
NEON unrolled 2-pass copy : 738.3 MB/s (0.4%)
NEON unrolled 2-pass copy prefetched (32 bytes step) : 682.1 MB/s (0.3%)
NEON unrolled 2-pass copy prefetched (64 bytes step) : 733.7 MB/s (0.3%)
NEON fill : 2668.8 MB/s (0.1%)
NEON fill backwards : 2668.8 MB/s
VFP copy : 1086.0 MB/s (0.3%)
VFP 2-pass copy : 747.6 MB/s
ARM fill (STRD) : 2497.3 MB/s (0.3%)
ARM fill (STM with 8 registers) : 2668.8 MB/s
ARM fill (STM with 4 registers) : 2666.8 MB/s
ARM copy prefetched (incr pld) : 1035.4 MB/s (0.4%)
ARM copy prefetched (wrap pld) : 1081.5 MB/s (0.2%)
ARM 2-pass copy prefetched (incr pld) : 829.6 MB/s (0.3%)
ARM 2-pass copy prefetched (wrap pld) : 798.4 MB/s
==========================================================================
== Memory latency test ==
== ==
== Average time is measured for random memory accesses in the buffers ==
== of different sizes. The larger is the buffer, the more significant ==
== are relative contributions of TLB, L1/L2 cache misses and SDRAM ==
== accesses. For extremely large buffer sizes we are expecting to see ==
== page table walk with several requests to SDRAM for almost every ==
== memory access (though 64MiB is not nearly large enough to experience ==
== this effect to its fullest). ==
== ==
== Note 1: All the numbers are representing extra time, which needs to ==
== be added to L1 cache latency. The cycle timings for L1 cache ==
== latency can be usually found in the processor documentation. ==
== Note 2: Dual random read means that we are simultaneously performing ==
== two independent memory accesses at a time. In the case if ==
== the memory subsystem can't handle multiple outstanding ==
== requests, dual random read has the same timings as two ==
== single reads performed one after another. ==
==========================================================================
block size : single random read / dual random read
1024 : 0.0 ns / 0.0 ns
2048 : 0.0 ns / 0.0 ns
4096 : 0.0 ns / 0.0 ns
8192 : 0.0 ns / 0.0 ns
16384 : 0.0 ns / 0.0 ns
32768 : 0.0 ns / 0.0 ns
65536 : 6.2 ns / 10.3 ns
131072 : 9.6 ns / 14.6 ns
262144 : 12.3 ns / 17.5 ns
524288 : 86.0 ns / 134.6 ns
1048576 : 127.1 ns / 175.4 ns
2097152 : 154.5 ns / 195.5 ns
4194304 : 168.7 ns / 204.2 ns
8388608 : 177.7 ns / 211.2 ns
16777216 : 187.7 ns / 224.2 ns
33554432 : 201.5 ns / 248.2 ns
67108864 : 225.5 ns / 295.6 ns