Cavium ThunderX - ssvb/tinymembench GitHub Wiki
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tinymembench v0.3.9 (simple benchmark for memory throughput and latency)
==========================================================================
== Memory bandwidth tests ==
== ==
== Note 1: 1MB = 1000000 bytes ==
== Note 2: Results for 'copy' tests show how many bytes can be ==
== copied per second (adding together read and writen ==
== bytes would have provided twice higher numbers) ==
== Note 3: 2-pass copy means that we are using a small temporary buffer ==
== to first fetch data into it, and only then write it to the ==
== destination (source -> L1 cache, L1 cache -> destination) ==
== Note 4: If sample standard deviation exceeds 0.1%, it is shown in ==
== brackets ==
==========================================================================
C copy backwards : 1098.1 MB/s (0.2%)
C copy : 1095.4 MB/s
C copy prefetched (32 bytes step) : 1094.7 MB/s
C copy prefetched (64 bytes step) : 1095.0 MB/s
C 2-pass copy : 945.5 MB/s
C 2-pass copy prefetched (32 bytes step) : 945.7 MB/s
C 2-pass copy prefetched (64 bytes step) : 945.6 MB/s (0.1%)
C fill : 9735.4 MB/s
---
standard memcpy : 1237.0 MB/s
standard memset : 12925.5 MB/s
==========================================================================
== Memory latency test ==
== ==
== Average time is measured for random memory accesses in the buffers ==
== of different sizes. The larger is the buffer, the more significant ==
== are relative contributions of TLB, L1/L2 cache misses and SDRAM ==
== accesses. For extremely large buffer sizes we are expecting to see ==
== page table walk with several requests to SDRAM for almost every ==
== memory access (though 64MiB is not nearly large enough to experience ==
== this effect to its fullest). ==
== ==
== Note 1: All the numbers are representing extra time, which needs to ==
== be added to L1 cache latency. The cycle timings for L1 cache ==
== latency can be usually found in the processor documentation. ==
== Note 2: Dual random read means that we are simultaneously performing ==
== two independent memory accesses at a time. In the case if ==
== the memory subsystem can't handle multiple outstanding ==
== requests, dual random read has the same timings as two ==
== single reads performed one after another. ==
==========================================================================
block size : single random read / dual random read, [MADV_NOHUGEPAGE]
1024 : 0.0 ns / 0.0 ns
2048 : 0.0 ns / 0.0 ns
4096 : 0.0 ns / 0.0 ns
8192 : 0.0 ns / 0.0 ns
16384 : 0.0 ns / 0.0 ns
32768 : 0.0 ns / 0.0 ns
65536 : 9.6 ns / 19.9 ns
131072 : 14.4 ns / 29.9 ns
262144 : 16.7 ns / 34.8 ns
524288 : 18.0 ns / 37.3 ns
1048576 : 18.6 ns / 38.6 ns
2097152 : 18.9 ns / 39.2 ns
4194304 : 23.3 ns / 48.0 ns
8388608 : 25.7 ns / 52.9 ns
16777216 : 71.7 ns / 139.9 ns
33554432 : 116.4 ns / 232.8 ns
67108864 : 141.5 ns / 283.0 ns
block size : single random read / dual random read, [MADV_HUGEPAGE]
1024 : 0.0 ns / 0.0 ns
2048 : 0.0 ns / 0.0 ns
4096 : 0.0 ns / 0.0 ns
8192 : 0.0 ns / 0.0 ns
16384 : 0.0 ns / 0.0 ns
32768 : 0.0 ns / 0.0 ns
65536 : 9.6 ns / 19.9 ns
131072 : 14.3 ns / 29.9 ns
262144 : 16.7 ns / 34.8 ns
524288 : 18.0 ns / 37.3 ns
1048576 : 18.6 ns / 38.6 ns
2097152 : 18.9 ns / 39.2 ns
4194304 : 23.3 ns / 48.0 ns
8388608 : 26.1 ns / 52.8 ns
16777216 : 71.2 ns / 144.6 ns
33554432 : 114.8 ns / 231.8 ns
67108864 : 140.6 ns / 282.6 ns