BeagleBone Black (AM3358) - ssvb/tinymembench GitHub Wiki
BeagleBone Black (rev C)
Texas Instruments AM3358 r2.1 SoC
ARM Cortex-A8 r3p2 @ 1 GHz
32 KB data L1 cache (128 sets × 4 ways × 64 bytes)
256 KB unified L2 cache (512 sets × 8 ways × 64 bytes)
16-bit DDR3-800 memory interface
tinymembench v0.4.9 (simple benchmark for memory throughput and latency)
==========================================================================
== Memory bandwidth tests ==
== ==
== Note 1: 1MB = 1000000 bytes ==
== Note 2: Results for 'copy' tests show how many bytes can be ==
== copied per second (adding together read and writen ==
== bytes would have provided twice higher numbers) ==
== Note 3: 2-pass copy means that we are using a small temporary buffer ==
== to first fetch data into it, and only then write it to the ==
== destination (source -> L1 cache, L1 cache -> destination) ==
== Note 4: If sample standard deviation exceeds 0.1%, it is shown in ==
== brackets ==
==========================================================================
C copy backwards : 198.4 MB/s (0.3%)
C copy backwards (32 byte blocks) : 201.8 MB/s (0.2%)
C copy backwards (64 byte blocks) : 201.8 MB/s (0.1%)
C copy : 230.0 MB/s
C copy prefetched (32 bytes step) : 505.1 MB/s
C copy prefetched (64 bytes step) : 475.2 MB/s
C 2-pass copy : 218.0 MB/s
C 2-pass copy prefetched (32 bytes step) : 428.1 MB/s (0.2%)
C 2-pass copy prefetched (64 bytes step) : 402.5 MB/s
C fill : 1511.9 MB/s
C fill (shuffle within 16 byte blocks) : 1511.4 MB/s
C fill (shuffle within 32 byte blocks) : 1511.9 MB/s
C fill (shuffle within 64 byte blocks) : 1015.1 MB/s
---
standard memcpy : 258.3 MB/s (0.1%)
standard memset : 1511.9 MB/s
---
NEON read : 845.4 MB/s
NEON read prefetched (32 bytes step) : 671.7 MB/s
NEON read prefetched (64 bytes step) : 675.4 MB/s
NEON read 2 data streams : 947.3 MB/s (0.1%)
NEON read 2 data streams prefetched (32 bytes step) : 700.0 MB/s
NEON read 2 data streams prefetched (64 bytes step) : 714.3 MB/s
NEON copy : 544.9 MB/s
NEON copy prefetched (32 bytes step) : 563.5 MB/s
NEON copy prefetched (64 bytes step) : 549.0 MB/s (0.1%)
NEON unrolled copy : 548.9 MB/s
NEON unrolled copy prefetched (32 bytes step) : 566.9 MB/s
NEON unrolled copy prefetched (64 bytes step) : 539.2 MB/s
NEON copy backwards : 544.1 MB/s
NEON copy backwards prefetched (32 bytes step) : 564.4 MB/s
NEON copy backwards prefetched (64 bytes step) : 548.3 MB/s
NEON 2-pass copy : 498.2 MB/s
NEON 2-pass copy prefetched (32 bytes step) : 468.2 MB/s
NEON 2-pass copy prefetched (64 bytes step) : 471.1 MB/s
NEON unrolled 2-pass copy : 502.8 MB/s
NEON unrolled 2-pass copy prefetched (32 bytes step) : 449.5 MB/s
NEON unrolled 2-pass copy prefetched (64 bytes step) : 451.8 MB/s
NEON fill : 1510.7 MB/s
NEON fill backwards : 1511.5 MB/s
VFP copy : 390.9 MB/s
VFP 2-pass copy : 341.9 MB/s
ARM fill (STRD) : 1510.6 MB/s
ARM fill (STM with 8 registers) : 1512.0 MB/s (0.1%)
ARM fill (STM with 4 registers) : 1511.9 MB/s
ARM copy prefetched (incr pld) : 497.6 MB/s
ARM copy prefetched (wrap pld) : 508.4 MB/s
ARM 2-pass copy prefetched (incr pld) : 420.3 MB/s
ARM 2-pass copy prefetched (wrap pld) : 412.1 MB/s (0.2%)
==========================================================================
== Memory latency test ==
== ==
== Average time is measured for random memory accesses in the buffers ==
== of different sizes. The larger is the buffer, the more significant ==
== are relative contributions of TLB, L1/L2 cache misses and SDRAM ==
== accesses. For extremely large buffer sizes we are expecting to see ==
== page table walk with several requests to SDRAM for almost every ==
== memory access (though 64MiB is not nearly large enough to experience ==
== this effect to its fullest). ==
== ==
== Note 1: All the numbers are representing extra time, which needs to ==
== be added to L1 cache latency. The cycle timings for L1 cache ==
== latency can be usually found in the processor documentation. ==
== Note 2: Dual random read means that we are simultaneously performing ==
== two independent memory accesses at a time. In the case if ==
== the memory subsystem can't handle multiple outstanding ==
== requests, dual random read has the same timings as two ==
== single reads performed one after another. ==
==========================================================================
block size : single random read / dual random read
1024 : 0.0 ns / 0.0 ns
2048 : 0.0 ns / 0.0 ns
4096 : 0.0 ns / 0.0 ns
8192 : 0.0 ns / 0.0 ns
16384 : 0.0 ns / 0.0 ns
32768 : 0.0 ns / 0.0 ns
65536 : 4.5 ns / 9.0 ns
131072 : 9.2 ns / 18.6 ns
262144 : 33.2 ns / 60.3 ns
524288 : 144.7 ns / 288.5 ns
1048576 : 202.3 ns / 404.4 ns
2097152 : 232.4 ns / 464.2 ns
4194304 : 248.9 ns / 496.8 ns
8388608 : 260.0 ns / 518.4 ns
16777216 : 269.8 ns / 538.3 ns
33554432 : 289.7 ns / 578.2 ns
67108864 : 322.2 ns / 643.4 ns