system type : Broadcom BCM4716 chip rev 1 pkg 10
processor : 0
cpu model : MIPS 74K V4.0
BogoMIPS : 238.20
cpu MHz : 480
wait instruction : no
microsecond timers : yes
tlb_entries : 64
extra interrupt vector : no
hardware watchpoint : yes
ASEs implemented : mips16 dsp
shadow register sets : 1
VCED exceptions : not available
VCEI exceptions : not available
unaligned_instructions : 0
tinymembench v0.2.9 (simple benchmark for memory throughput and latency)
==========================================================================
== Memory bandwidth tests ==
== ==
== Note 1: 1MB = 1000000 bytes ==
== Note 2: Results for 'copy' tests show how many bytes can be ==
== copied per second (adding together read and writen ==
== bytes would have provided twice higher numbers) ==
== Note 3: 2-pass copy means that we are using a small temporary buffer ==
== to first fetch data into it, and only then write it to the ==
== destination (source -> L1 cache, L1 cache -> destination) ==
== Note 4: If sample standard deviation exceeds 0.1%, it is shown in ==
== brackets ==
==========================================================================
C copy backwards : 113.7 MB/s (0.7%)
C copy : 115.2 MB/s (0.5%)
C copy prefetched (32 bytes step) : 188.1 MB/s (1.0%)
C copy prefetched (64 bytes step) : 189.1 MB/s (1.1%)
C 2-pass copy : 109.2 MB/s (2.4%)
C 2-pass copy prefetched (32 bytes step) : 152.5 MB/s (1.5%)
C 2-pass copy prefetched (64 bytes step) : 154.5 MB/s (1.5%)
C fill : 407.1 MB/s (0.8%)
---
standard memcpy : 121.6 MB/s (0.5%)
standard memset : 331.2 MB/s (4.4%)
---
MIPS32 copy prefetched (32 bytes step) : 355.5 MB/s (2.1%)
MIPS32 2-pass copy prefetched (32 bytes step) : 254.8 MB/s (1.0%)
MIPS32 fill prefetched (32 bytes step) : 797.1 MB/s (1.6%)
==========================================================================
== Memory latency test ==
== ==
== Average time is measured for random memory accesses in the buffers ==
== of different sizes. The larger is the buffer, the more significant ==
== are relative contributions of TLB, L1/L2 cache misses and SDRAM ==
== accesses. For extremely large buffer sizes we are expecting to see ==
== page table walk with total 3 requests to SDRAM for almost every ==
== memory access (though 64MiB is not large enough to experience this ==
== effect to its fullest). ==
== ==
== Note 1: All the numbers are representing extra time, which needs to ==
== be added to L1 cache latency. The cycle timings for L1 cache ==
== latency can be usually found in the processor documentation. ==
== Note 1: Dual random read means that we are simultaneously performing ==
== two independent memory accesses at a time. In the case if ==
== the memory subsystem can't handle multiple outstanding ==
== requests, dual random read has the same timings as two ==
== single reads performed one after another. ==
==========================================================================
block size : read access time (single random read / dual random read)
2 : 0.0 ns / 0.0 ns
4 : 0.2 ns / 0.3 ns
8 : 0.1 ns / 0.3 ns
16 : 0.2 ns / 0.0 ns
32 : 0.2 ns / 0.0 ns
64 : 0.2 ns / 0.1 ns
128 : 0.3 ns / 0.2 ns
256 : 0.2 ns / 0.2 ns
512 : 0.2 ns / 0.2 ns
1024 : 0.1 ns / 0.3 ns
2048 : 0.0 ns / 0.1 ns
4096 : 0.2 ns / 0.0 ns
8192 : 0.3 ns / 0.3 ns
16384 : 0.2 ns / 0.2 ns
32768 : 3.0 ns / 4.8 ns
65536 : 92.0 ns / 147.1 ns
131072 : 141.3 ns / 196.3 ns
262144 : 167.6 ns / 215.8 ns
524288 : 186.4 ns / 234.0 ns
1048576 : 296.7 ns / 430.9 ns
2097152 : 351.7 ns / 530.6 ns
4194304 : 382.0 ns / 589.5 ns
8388608 : 409.0 ns / 638.6 ns
16777216 : 454.4 ns / 731.7 ns
33554432 : 512.5 ns / 842.7 ns
67108864 : 554.9 ns / 927.1 ns